ISL75051SEH INTERSIL [Intersil Corporation], ISL75051SEH Datasheet
ISL75051SEH
Related parts for ISL75051SEH
ISL75051SEH Summary of contents
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... Rad Hard, Positive, Ultra Low Dropout Regulator ISL75051SEH The ISL75051SEH is a radiation hardened low-voltage, high-current, single-output LDO specified for up to 3.0A of continuous output current. These devices operate over an input voltage range of 2.2V to 6.0V and are capable of providing output voltages of 0.8V to 5.0V adjustable based on resistor divider setting ...
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... ISL75051SEH 520MV REFERENCE BIAS 450mV EN 10 BYP 9 511 OCP 11 8 ADJ VIN 12 VOUT 7 VIN 13 6 VOUT VIN 14 VOUT 5 ISL75051SEH VOUT VIN 15 4 VIN 3 VOUT 16 VIN 17 VOUT 2 PG GND 18 1 0.1µF 4.32k VIN 2.26k 5.49k CURRENT OCP LIMIT ADJ POWER PMOS VOUT ...
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... These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISL75051SEH. For more information on MSL please see Tech Brief TB363. 3 ...
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... DC Input Line Regulation DC Input Line Regulation DC Input Line Regulation DC Input Line Regulation DC Output Load Regulation DC Output Load Regulation 4 ISL75051SEH Thermal Information Thermal Resistance (Typical CDFP Package (Notes Storage Temperature Range .-65°C to +150°C Radiation Information (Note 4) Maximum Total Dose Dose Rate = 50-300rad(Si)/s ...
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... DEVICE START-UP CHARACTERISTICS: ENABLE PIN Rising Threshold Falling Threshold Enable Pin Leakage Current Enable Pin Propagation Delay Enable Pin Turn-on Delay Enable Pin Turn-on Delay Hysteresis 5 ISL75051SEH = 220µF 25mΩ and 0.1µF X7R +25° defines guaranteed limits TEST CONDITIONS V = 5.0V ...
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... DC Output Voltage Accuracy 17 VADJ Pin Voltage 18 VADJ Pin Voltage 19 VADJ Pin Voltage 20 VADJ Pin Voltage 21 VADJ Pin Voltage 6 ISL75051SEH = 220µF 25mΩ and 0.1µF X7R +25° defines guaranteed limits TEST CONDITIONS 2.2V < VIN < 6.0V 2.2V < VIN < 6.0V 2.2V < VIN < 6.0V ...
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... Enable Falling Threshold 52 Enable Pin Leakage Current 53 Enable Pin Leakage Current 54 Enable Hysterisis 55 Enable Hysterisis 56 Enable Pin Propagation Delay 57 PG Rising Threshold 58 PG Rising Threshold 59 PG Falling Threshold 7 ISL75051SEH T = +25°C, unless otherwise noted. A CONDITION V = 1.5V 5.5V OUT 1.8V 2.2V OUT 1.8V 3.6V OUT ...
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... VADJ Pin Voltage 22 VADJ Pin Voltage 23 VADJ Pin Voltage 24 VADJ Pin Voltage 25 VADJ Pin Voltage 26 VADJ Pin Voltage 27 VADJ Pin Voltage 28 DC Input Line Regulation 29 DC Input Line Regulation 8 ISL75051SEH T = +25°C, unless otherwise noted. A CONDITION 1mA SINK I ...
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... PG Falling Threshold 60 PG Falling Threshold 61 PG Hysteresis 62 PG Hysteresis 63 PG Low Voltage 64 PG Low Voltage 65 PG Leakage Current NOTE: 14. See the Radiation report. 9 ISL75051SEH T = +25°C, unless otherwise noted. A CONDITION V + 0.4V < V < 6.0V 5.0V OUT IN OUT V = 1.5V; 0A < I < 3.0A OUT LOAD IN OUT V = 1.8V ...
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... SPEC LIMIT 7 HDR BIAS LDR BIAS 6 LDR GROUND 5 HDR GROUND SPEC LIMIT 100 TOTAL DOSE, krad(Si) FIGURE 7. OUTPUT SHORT CIRCUIT CURRENT ISL75051SEH HDR BIAS 150 POST ANNEAL , 3.6V NO LOAD FIGURE 4. DC OUTPUT VOLTAGE, 1.5V OUT IN HDR BIAS HDR GROUND 150 POST ANNEAL , 6. LOAD FIGURE 6 ...
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... FIGURE 11. LOAD REGULATION, V 4.090 4.085 +128°C, V OUT 4.080 4.075 4.070 -58°C, V OUT 4.065 OUT 4.060 0.0 0.5 1.0 1.5 I (A) OUT FIGURE 13. LOAD REGULATION ISL75051SEH +128°C, V OUT 2.5 3.0 3 OUT OUT OUT OUT OUT 2.5 3.0 3 OUT OUT +25°C, V OUT 2.0 2.5 3.0 3 OUT OUT 0.522 +25° ...
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... OCP 2.61k OCP OCP 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 V (V) IN FIGURE 17 OCP AT +128°C, V OCP FIGURE 19. TRANSIENT LOAD RESPONSE 47µF, 35mΩ OUT 12 ISL75051SEH (Continued) +128°C, V ADJ 5.0 5.5 6.0 6.5 7.0 = 1.00k = 2.00k = 3. 5.11k OCP 5.5 6.0 6.5 7.0 = 1.5V OUT = 3.3V 2.5V, FIGURE 20. TRANSIENT LOAD RESPONSE OUT 0.511k ...
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... FIGURE 23. POWER-ON AND POWER-OFF +25° 6V 0.8V OUT OUT 1000 100 10 1 0.1 300 3k FREQUENCY (Hz) FIGURE 25. NOISE (µV/√Hz) 13 ISL75051SEH (Continued) FIGURE 22. POWER-ON AND POWER-OFF +25°C, = 0.5A, PGOOD TURN-ON FIGURE 24. POWER-ON AND POWER-OFF +25°C, = 0.5A, PGOOD TURN-OFF 30k 300k ...
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... At the lower limit of ESR = 6mΩ, the phase margin is about 51°C. On the high side, an ESR of 100mΩ is found to limit the gain margin at around 10dB. The typical GM/PM seen with capacitors are shown in Table 2. 14 ISL75051SEH TABLE 2. TYPICAL GM/PM WITH VARIOUS CAPACITORS CAPACITANCE (µF) 47 ...
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... VIN VIN I1 I2 90µAdc 0.5µAdc U1 +IN BYPASS INT SS NODE -IN EXT PIN -IN ISL75051SEH 0.1µF 50pF 0 0 FIGURE 29. SOFT-START 15 ISL75051SEH Current Limit Protection The RH LDO incorporates protection against overcurrent due to any short or overload condition applied to the output pin. The current limit circuit becomes a constant current source when the ...
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... VIN 1078 -2965 11 VIN 1078 -1853 12 VIN 1078 -711 13 PG 420 -25 16 ISL75051SEH BACKSIDE FINISH Silicon PROCESS 0.6µM BiCMOS Junction Isolated ASSEMBLY RELATED INFORMATION Substrate Potential Unbiased ADDITIONAL INFORMATION Worst Case Current Density 5 2 < A/cm Transistor Count 2932 Layout Characteristics Step and Repeat 4555µ ...
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... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 17 ISL75051SEH www.intersil.com/askourstaff http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree www.intersil.com/design/quality CHANGE www.intersil.com/products ISL75051SEH www.intersil.com for a FN8294.0 August 28, 2012 ...
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... LEAD FINISH 0.004 (0.102) 0.010 (0.254) BASE METAL 0.004 (0.102) 0.017 (0.432) 0.013 (0.330) 0.0015 (0.04) MAX 0.020 (0.508) 0.013 (0.330) 3 SECTION A-A 18 ISL75051SEH 0.015 (0.381) PIN NO. 1 0.005 (0.127 OPTIONAL PIN NO AREA TOP VIEW 0.038 (0.97) 0.397 (10.084) 6 0.026 (0.66) 0.377 (9.576) 0.283 (7.19) ...