ISL75051SEH INTERSIL [Intersil Corporation], ISL75051SEH Datasheet - Page 14

• Manufacturer Part Number: ISL75051SEH
• Description: 3A, Rad Hard, Positive, Ultra Low Dropout Regulator
• Manufacturer: INTERSIL [Intersil Corporation]

Applications Information
Input Voltage Requirements
This RH LDO will work from a V
input supply can have a tolerance of as much as ±10% for
conditions noted in the “Electrical Specifications” table starting
on page 4. Minimum guaranteed input voltage is 2.2V. However,
due to the nature of an LDO, V
than the output voltage, plus dropout at the maximum rated
current of the application, if active filtering (PSRR) is expected
from V
been generously specified to allow applications to design for
efficient operation.
Adjustable Output Voltage
The output voltage of the RH LDO can be set to any user
programmable level between 0.8V to 5.0V. This is achieved with
a resistor divider connected between the OUT, ADJ and GND pins.
With the internal reference at 0.52V, the divider ratio should be
fixed such that when the desired VOUT level is reached, the
voltage presented to the ADJ pin is 0.52V. Resistor values for
typical voltages are shown in Table 1.
Input and Output Capacitor Selection
RH operation requires the use of a combination of tantalum and
ceramic capacitors to achieve a good volume-to-capacitance
ratio. The recommended combination is a 220µF, 25mΩ 10V
DSSC 04051-032 rated tantalum capacitor in parallel with a
0.1µF MIL-PRF-49470 CDR04 ceramic capacitor, to be
connected between V
LDO, with PCB traces no longer than 0.5cm.
The stability of the device depends on the capacitance and ESR
of the output capacitor. The usable ESR range for the device is
6mΩ to 100mΩ. At the lower limit of ESR = 6mΩ, the phase
margin is about 51°C. On the high side, an ESR of 100mΩ is
found to limit the gain margin at around 10dB. The typical
GM/PM seen with capacitors are shown in Table 2.
V
0.8V
1.5V
1.8V
2.5V
4.0V
5.0V
IN
OUT
TABLE 1. RESISTOR VALUES FOR TYPICAL VOLTAGES
to V
OUT
. The dropout spec of this family of LDOs has
IN
R
BOTTOM
2.26k
1.13k
7.87k
1.74k
634
499
to GND pins and V
14
IN
IN
must be some margin higher
in the range of 2.2V to 6.0V. The
OUT
to GND pins of the
4.32k
4.32k
4.32k
4.32k
4.32k
4.32k
R
TOP
ISL75051SEH
Type numbers of KEMET capacitors used in the device are shown
in Table 3.
A typical gain phase plot measured on the ISL75051SRHEVAL1Z
evaluation board for V
220µF, 10V, 25mΩ capacitor is shown in Figure 27 and is
measured at GM = 16.3dB and PM = 69.16°.
Enable
The device can be enabled by applying a logic high on the EN pin.
The enable threshold is typically 0.9V. A soft-start cycle is
initiated when the device is enabled using this pin. Taking this pin
to logic low disables the device.
EN can be driven from either an open drain or a totem pole logic
drive between EN pin and GND. Assuming an open drain
configuration, M1 will actively pull down the EN line, as shown in
Figure 28, and thereby discharge the input capacitance, shutting
off the device immediately.
CAPACITANCE
-10
-20
-30
-40
-50
-60
T525D107M010ATE025
T530D227M010ATE006
T525D227M010ATE025
T525D476M016ATE035
60
50
40
30
20
10
T495X107K016ATE100
(µF)
100
220
220
100
KEMET TYPE NUMBER
0
500
47
TABLE 2. TYPICAL GM/PM WITH VARIOUS CAPACITORS
3.3V
1.8V
3.0A
1x220µF
T525D
TABLE 3. KEMET CAPACITORS USED IN DEVICE
FIGURE 27. TYPICAL GAIN PHASE PLOT
5k
IN
(mΩ)
ESR
100
35
25
25
6
= 3.3V, V
FREQUENCY (Hz)
GAIN
50k
OUT
GAIN MARGIN
PHASE
= 1.8V and I
(dB)
14
16
19
16
10
CAPACITOR DETAILS
100µF, 16V, 100mΩ
500k
100µF, 10V, 25mΩ
220µF, 10V, 25mΩ
220µF, 10V, 6mΩ
47µF, 10V, 35mΩ
OUT
PHASE MARGIN
5M
August 28, 2012
= 3A with a
(°)
55
57
51
69
62
180
150
120
90
60
30
0
-30
-60
-90
-120
-150
-180
FN8294.0