ISL78010_11 INTERSIL [Intersil Corporation], ISL78010_11 Datasheet - Page 12

• Manufacturer Part Number: ISL78010_11
• Description: Automotive Grade TFT-LCD Power Supply
• Manufacturer: INTERSIL [Intersil Corporation]

Larger values of R
A
ensure A
maximum desired current and then the transient load
response of A
maximum value of R
Operation of the DELB Output Function
An open drain DELB output is provided to allow the boost
output voltage, developed at C
Diagram” on page 18), to be delayed via an external switch
(Q
charge pump supply have achieved regulation during the
start-up sequence shown in Figures 14 and 16. This then
allows the A
instead of the normal offset voltage of V
were not present.
When DELB is activated by the start-up sequencer, it sinks
50µA, allowing a controlled turn-on of Q
C
reduce in-rush current into C
by R
required by the voltage rating of this device. When the
voltage at DELB falls to less than 0.6V, the sink current is
increased to ~1.2mA to firmly pull DELB to 0V.
The voltage at DELB is monitored by the fault protection
circuit so that if the initial 50µA sink current fails to pull DELB
below ~0.6V after the start-up sequencing has completed,
then a fault condition will be detected and a fault time-out
ramp will be initiated on the C
Operation of the PG Output Function
The PG output consists of an internal pull-up PMOS device to
V
current-limited pull-down NMOS device which sinks ~15µA,
allowing a controlled turn-on of Q
used to control how fast Q
current into C
than 0.6V, the PG sink current is increased to ~1.2mA to firmly
pull the pin to 0V.
The voltage at PG is monitored by the fault protection circuit
so that if the initial 15µA sink current fails to pull PG below
~0.6V after the start-up sequencing has completed, then a
fault condition will be detected, and a fault time-out ramp will
be initiated on the C
Cascaded MOSFET Application
A 20V N-Channel MOSFET is integrated in the boost
regulator. For applications where the output voltage is
greater than 20V, an external cascaded MOSFET is needed
as shown in Figure 22. The voltage rating of the external
MOSFET should be greater than V
VDD
IN
9
4
. C
, to turn off the external Q
) to a time after the V
9
16
load currents less than the current limit are used. To
and R
can be used to control the turn-on time of Q
VDD
VDD
8
1
stability, the IC should be operated at the
VDD
can be used to limit the V
. When the voltage at the PG pin falls to less
and V
INT
should be used to determine the
DEL
INT
(R
ON
.
BOOST
capacitor (C
7
1
) may be possible if maximum
supplies to start-up from 0V
turns on and limiting inrush
1
9
12
DEL
. The potential divider formed
protection switch, and a
2
(see “Typical Application
supply and negative V
1
gate capacitance. C
capacitor (C
BOOST
7
).
IN
GS
4
-V
and charge-up of
.
voltage of Q
DIODE
7
).
(D
4
1
O
) if Q
to
OFF
4
is
if
ISL78010
4
Linear-Regulator Controllers (V
V
The ISL78010 includes three independent linear-regulator
controllers, in which two are positive output voltage (V
and V
V
shown in Figures 23, 24, and 25, respectively.
Calculation of the Linear Regulator Base-Emitter
Resistors (R
For the pass transistor of the linear regulator, low frequency
gain (h
in the datasheet. The pass transistor adds a pole to the loop
transfer function at f
maintain phase margin at low frequency, the best choice for
a pass device is often a high-frequency, low-gain switching
transistor. Further improvement can be obtained by adding a
base-emitter resistor R
Block Diagrams on page 13), which increase the pole
frequency to f
re = KT/qIc. Choose the lowest value R
long as there is still enough base current (I
maximum output current (I
For example, if in the V
FMMT549 PNP transistor is used as the external pass
transistor (Q
maximum V
sheet indicates h
The base-emitter saturation voltage is Vbe_max = 1.25V.
Note that this is normally Vbe ~ 0.7V; however, for the Q
transistor, an internal Darlington arrangement is used to
increase its current gain, giving a “base-emitter” voltage of
2 x V
Note also that using a high current Darlington PNP transistor
for Q
voltage be required, then an ordinary high-gain PNP
transistor should be selected for Q
collector-emitter saturation voltage.
LOGIC
FIGURE 22. CASCADED MOSFET TOPOLOGY FOR HIGH
OFF
V
IN
5
BE
LOGIC
)
requires that V
FE
.
linear-regulator controller functional diagrams are
) and unity gain frequency (f
LOGIC
) and one is negative. The V
5
OUTPUT VOLTAGE APPLICATIONS
p
in the application diagram), then for a
BL
= f
ISL78010
FE
, R
T
operating requirement of 500mA, the data
*(1+ h
(min) = 100.
p
BP
IN
= f
BE
LOGIC
> V
T
and R
FE
/h
(R
C
LOGIC
FE
).
*re/R
BP
LX
. Therefore, in order to
linear regulator, a Fairchild
, R
BN
BE
BL
+ 2V. Should a lower input
5
)
to allow a lower
, R
)/h
T
ON
FB
) are usually specified
FE
BN
BE
ON
, V
, where
in the design as
B
in the Functional
, V
LOGIC
) to support the
OFF
, and
, and
May 3, 2011
V
BOOST
FN6501.1
ON
5