ISL78420 INTERSIL [Intersil Corporation], ISL78420 Datasheet - Page 10

• Manufacturer Part Number: ISL78420
• Description: 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time
• Manufacturer: INTERSIL [Intersil Corporation]

to the source of the high-side FET, the HS node will rise almost to
the level of the bridge voltage (less the conduction voltage across
the bridge FET). Because the boot capacitor voltage is referenced
to the source voltage of the high-side FET, the HB node is V
volts above the HS node and the boot diode is reversed biased.
Because the high-side driver circuit is referenced to the HS node,
the HO output is now approximately VHB + VBRIDGE above
ground.
During the low to high transition of the HS node, the boot
capacitor sources the necessary gate charge to fully enhance the
high-side bridge FET gate. After the gate is fully charged, the boot
capacitor no longer sources the charge to the gate but continues
to provide bias current to the high-side driver. It is clear that the
charge of the boot capacitor must be substantially larger than
the required charge of the high-side FET and high-side driver
otherwise the boot voltage will sag excessively. If the boot
capacitor value is too small for the required maximum of on-time
of the high-side FET, the high-side UV lockout may engage
resulting with an unexpected operation.
Application Information
Selecting the Boot Capacitor Value
The boot capacitor value is chosen not only to supply the internal
bias current of the high-side driver but also, and more
significantly, to provide the gate charge of the driven FET without
causing the boot voltage to sag excessively. In practice, the boot
capacitor should have a total charge that is approximately 20x
the gate charge of the driven power FET for a 5% drop in voltage
after the charge has been transferred from the boot capacitor to
the gate capacitance.
The following parameters are required to calculate the value of
the boot capacitor for a specific amount of voltage droop. In this
example, the values used are arbitrary. They should be changed
to comply with the actual application.
V
V
Period = 1ms
I
R
Ripple= 5%
I
Qgate80V = 64nC
HB
gate_leak
DD
HB
GS
= 100µA
= V
= 10V
= 100kΩ
DD
= 100nA
- 0.6V = V
HO
V
High side driver bias voltage (V
voltage) referenced to V
This is the longest expected switching period
Worst case high side driver current when
xHO = high (this value is specified for V
12V but the error is not significant)
Gate-source resistor (usually not needed)
Desired ripple voltage on the boot cap (larger
ripple is not recommended)
From the FET vendor’s datasheet
From Figure 18
DD
can be any value between 7 and 14VDC
10
HS
DD
- boot diode
DD
ISL78420
DD
=
The following equations calculate the total charge required for
the Period. These equations assume that all of the parameters
are constant during the period duration. The error is insignificant
if the ripple is small.
C
C
If the gate to source resistor is removed (R
needed or recommended), then:
C
Q
boot
boot
boot
C
=
Q
= 0.33µF
=
=
gate80V
FIGURE 18. TYPICAL GATE CHARGE OF A POWER FET
Q
0.52μF
12
10
C
8
6
4
2
0
0
⁄
(
Ripple ∗ VDD
I
D
+
10
= 33A
Period
V
DS
= 20V
QG TOTAL GATE CHARGE (nC)
20
V
×
DS
I
HB
)
= 50V
30
+
V
V
DS
HO
40
= 80V
⁄
(
R
50
GS
GS
+
60
I
gate_leak
is usually not
September 24, 2012
70
)
80
FN8296.1
(EQ. 1)
(EQ. 2)