ISL78420 INTERSIL [Intersil Corporation], ISL78420 Datasheet - Page 2

• Manufacturer Part Number: ISL78420
• Description: 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time
• Manufacturer: INTERSIL [Intersil Corporation]

Block Diagram
Pin Configurations
VDD
VDD
HO
HB
HS
NC
HO
HB
HS
PWM
VDD
RDT
EN
1
2
3
4
5
1
3
4
5
(10 LD 4X4 TDFN)
ISL78420ARTBZ
ISL78420ARTAZ
(9 LD 4X4 TDFN)
TOP VIEW
TOP VIEW
EPAD
EPAD
5V
2
+
+
-
-
5V
210k
10
10
9
8
7
6
9
8
7
6
LO
VSS
PWM
EN
RDT
LO
VSS
PWM
EN
RDT
ISL78420
VOLTAGE
UNDER
EPAD
DELAY
DELAY
Pin Descriptions
10
LD
10 10
1
2
3
4
8
7
9
5
6
-
LD SYMBOL
9
1
3
4
5
8
7
9
6
-
-
LEVEL
SHIFT
EPAD
PWM
VDD
RDT
VSS
HO
HB
HS
EN
NC
LO
VOLTAGE
UNDER
ISL78420
Positive supply voltage for lower gate driver.
Decouple this pin to ground with a 4.7µF or larger
ceramic capacitor to VSS
High-side bootstrap supply voltage referenced to
HS. Connect bootstrap capacitor to this pin and HS.
High-side output connected to gate of high-side FET.
High-side source connect to source of high-side FET.
Connect bootstrap capacitor to this pin and HB.
PWM input. For PWM = 5V, HO = 1, LO = 0. For
PWM = 0V, HO = 0, LO = 1. For PWM = 2.5V,
HO = LO = 0.
Output enable, when low, HO = LO = 0
Negative voltage supply, Connected to ground.
Low-side output. Connect to gate of low-side FET.
No Connect. This pin is isolated from all other pins.
May optionally be connected to VSS. Note that on
the 9 Ld package, there is no pin present at the
location normally occupied by pin 2.
A resistor connected between this pin and VSS adds
dead time by adding delay time to the falling and
rising edges of the PWM input.
The epad is electrically isolated. It is recommended
that the epad be connected to the VSS plane for
heat removal.
DESCRIPTION
HB
HO
HS
LO
VSS
September 24, 2012
FN8296.1