XCR3064A-10CP56C XILINX [Xilinx, Inc], XCR3064A-10CP56C Datasheet

XCR3064A-10CP56C

Manufacturer Part Number

XCR3064A-10CP56C

Description

64 Macrocell CPLD With Enhanced Clocking

Manufacturer

XILINX [Xilinx, Inc]

Datasheet

1.XCR3064A-10CP56C.pdf (18 pages)

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DS037 (v1.1) February 10, 2000

Features

• Industry's first TotalCMOS™ PLD - both CMOS design

• Fast Zero Power (FZP™) design technique provides

• 3V, In-System Programmable (ISP) using a JTAG

• High speed pin-to-pin delays of 7.5 ns

• Ultra-low static power of less than 100 µ A

• 5V tolerant I/Os to support mixed Voltage systems

• 100% routable with 100% utilization while all pins and

• Deterministic timing model that is extremely simple to

• Up to 12 clocks with programmable polarity at every

• Support for complex asynchronous clocking

• Innovative XPLA™ architecture combines high speed

• 1000 erase/program cycles guaranteed

• 20 years data retention guaranteed

• Logic expandable to 37 product terms

• Advanced 0.35 µ E

• Security bit prevents unauthorized access

• Design entry and verification using industry standard

• Reprogrammable using industry standard device

• Innovative Control Term structure provides either sum

• Programmable global 3-state pin facilitates `bed of

• Available in PLCC, VQFP, and Chip Scale BGA

• Industrial grade operates from 2.7V to 3.6V

DS037 (v1.1) February 10, 2000

and process technologies

ultra-low power and very high speed

interface

- On-chip superVoltage generation

- ISP commands include: Enable, Erase, Program,

- Supported by multiple ISP programming platforms

- Four pin JTAG interface (TCK, TMS, TDI, TDO)

- JTAG commands include: Bypass, Idcode

all macrocells are fixed

use

macrocell

with extreme flexibility

and Xilinx CAE tools

programmers

terms or product terms in each logic block for:

- Programmable 3-state buffer

- Asynchronous macrocell register preset/reset

- Up to two asynchronous clocks

nails' testing without using logic resources

packages

Verify

CMOS process

www.xilinx.com

1-800-255-7778

14*

XCR3064A: 64 Macrocell CPLD With

Enhanced Clocking

Product Specification

Description

The XCR3064A CPLD (Complex Programmable Logic

Device) is the second in a family of CoolRunner™ CPLDs

from Xilinx. These devices combine high speed and zero

power in a 64 macrocell CPLD. With the FZP design tech-

nique, the XCR3064A offers true pin-to-pin speeds of 7.5

ns, while simultaneously delivering power that is less than

100 µ A at standby without the need for "turbo bits" or other

power down schemes. By replacing conventional sense

amplifier methods for implementing product terms (a tech-

nique that has been used in PLDs since the bipolar era)

with a cascaded chain of pure CMOS gates, the dynamic

power is also substantially lower than any competing

CPLD. These devices are the first TotalCMOS PLDs, as

they use both a CMOS process technology and the pat-

ented full CMOS FZP design technique.

The Xilinx FZP CPLDs utilize the patented XPLA

(eXtended Programmable Logic Array) architecture. The

XPLA architecture combines the best features of both PLA

and PAL type structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA structure in

each logic block provides a fast 7.5 ns PAL path with five

dedicated product terms per output. This PAL path is joined

by an additional PLA structure that deploys a pool of 32

product terms to a fully programmable OR array that can

allocate the PLA product terms to any output in the logic

block. This combination allows logic to be allocated effi-

ciently throughout the logic block and supports as many as

37 product terms on an output. The speed with which logic

is allocated from the PLA array to an output is only 1.5 ns,

regardless of the number of PLA product terms used, which

results in worst case t

other pin. In addition, logic that is common to multiple out-

puts can be placed on a single PLA product term and

shared across multiple outputs via the OR array, effectively

increasing design density.

The XCR3064A CPLDs are supported by industry standard

CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Syn-

opsys, Synario, Viewlogic, and Synplicity), using text

(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-

ification uses industry standard simulators for functional

and timing simulation. Development is supported on per-

sonal computer, Sparc, and HP platforms. Device fitting

uses a Xilinx developed tool, XPLA Professional (available

on the Xilinx web site).

's of only 9.0 ns from any pin to any

Related parts for XCR3064A-10CP56C

XCR3064A-10CP56C Summary of contents

Page 1

... Xilinx. These devices combine high speed and zero power macrocell CPLD. With the FZP design tech- nique, the XCR3064A offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 µ standby without the need for "turbo bits" or other power down schemes ...

Page 2

... So the total pin-to-pin t product terms is 9.0 ns (7.5 ns for the PAL + 1.5 ns for the PLA LOGIC BLOCK ZIA 36 36 LOGIC BLOCK www.xilinx.com 1-800-255-7778 of the XCR3064A device PD for the XCR3064A using six MC0 MC1 I/O MC15 MC0 MC1 I/O MC15 SP00439 2 ...

Page 3

... XCR3064A: 64 Macrocell CPLD With Enhanced Clocking 36 ZIA INPUTS CONTROL 5 PAL ARRAY PLA ARRAY (32) Figure 2: Xilinx XPLA Logic Block Architecture 3 6 www.xilinx.com 1-800-255-7778 R SP00435A DS037 (v1.1) February 10, 2000 ...

Page 4

... R Macrocell Architecture Figure 3 shows the architecture of the macrocell used in the CoolRunner XCR3064A. The macrocell can be config- ured as either T-type flip-flop or a combinatorial logic function. A D-type flip-flop is generally more useful for implementing state machines and data buffering while a T-type flip-flop is generally more useful in implementing counters ...

Page 5

... In the XPLA architecture, the user knows up front whether the design will meet system timing requirements. This is due to the simplicity of the timing model. For example, in the XCR3064A device, the user knows up front that if a given output uses 5product terms or less, the t the t SU_PAL using six to 37 product terms, an additional 1 ...

Page 6

... JTAG specification is TRST* (Test Reset). TRST* is considered an optional signal, since it is not actually required to perform BST or ISP. The Xilinx XCR3064A saves an I/O pin for general purpose use by not implementing the optional TRST* signal in the JTAG inter- face. Instead, the Xilinx XCR3064A supports the test reset functionality through the use of its power up reset circuit, which is included in all Xilinx CPLDs ...

Page 7

... Serial input pin for instructions and test data. Data is shifted in on the rising edge of TCK. TDO Test Data Output Serial output pin for instructions and test data. Data is shifted out on the falling edge of TCK. The signal is tri-stated if data is not being shifted out of the device. Table 4: XCR3064A JTAG Pinout by Package Type Device XCR3064A TCK 44-pin PLCC ...

Page 8

... Note that an I/O macrocell used as buried logic that does not have the I/O pin used for input is considered to be unused, and the pull-down resistors will be turned on. We recommend that any unused I/O pins on the XCR3064A device be left unconnected. There are no on-chip pull-down structures associated with the dedicated input pins. Xilinx recommends that any unused dedicated inputs be terminated with external 10k Ω ...

Page 9

... XCR3064A: 64 Macrocell CPLD With Enhanced Clocking Programming Specifications Symbol DC Parameters V V supply program/verify CCP limit program/verify CCP CC V Input Voltage (High Input Voltage (Low Output Voltage (Low) SOL V Output Voltage (High) SOH TDO_I Output current (Low) OL TDO_I Output current (High) ...

Page 10

... This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. Inputs are tied This parameter guaranteed by design and characterization, not by test. DS037 (v1.1) February 10, 2000 XCR3064A: 64 Macrocell CPLD With Enhanced Clocking ≤ 3.6V CC Test Conditions ...

Page 11

... XCR3064A: 64 Macrocell CPLD With Enhanced Clocking AC Electrical Characteristics Commercial: 0 ° C ≤ T ≤ +70 ° C; 3.0V ≤ V AMB Symbol t Propagation delay time, input (or feedback node) to output through PAL PD_PAL t Propagation delay time, input (or feedback node) to output through PD_PLA PAL + PLA t Clock to out (global synchronous clock from pin) ...

Page 12

Page 13

... XCR3064A: 64 Macrocell CPLD With Enhanced Clocking AC Electrical Characteristics Industrial: -40 ° C ≤ T ≤ +85 ° C; 2.7V ≤ V AMB Symbol t Propagation delay time, input (or feedback node) to output through PAL PD_PAL t Propagation delay time, input (or feedback node) to output through PD_PLA PAL + PLA t Clock to out (global synchronous clock from pin) ...

Page 14

... PD_PAL (ns) 5.5 5.4 5.3 5 NUMBER OF OUTPUTS SWITCHING Figure 6: t vs. Output Switching PD_PAL DS037 (v1.1) February 10, 2000 XCR3064A: 64 Macrocell CPLD With Enhanced Clocking Component Measurement t PZH t PZL t P NOTE: For t and t PHZ measured 0.5V from steady-state active level. +3.0V 0V MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified ...

Page 15

... XCR3064A: 64 Macrocell CPLD With Enhanced Clocking Pin Function and Layout XCR3064 44-Pin PLCC and VQFP Package Pin # PLCC 1 IN1 2 IN3 I/O-A0-CK3 5 I/O-A2 6 I/O-A5 7 I/O-A8 8 I/O-A11 9 I/O-A12 10 GND 11 I/O-A13 12 I/O-A15 13 I/O-B15 (TMS) 14 I/O-B13 I/O-B10 17 I/O-B8 18 I/O-B4 19 I/O-B3 20 I/O-B2 21 I/O-B0/CK2 22 GND XCR3064A: 44-pin PLCC ...

Page 16

... I/O-D8 (TDO) XCR3064A: 56-ball Chup Scale BGA BOTTOM VIEW DS037 (v1.1) February 10, 2000 XCR3064A: 64 Macrocell CPLD With Enhanced Clocking Pkg Ball Function D1 I/0-A11 D3 I/0-A12 D8 I/0-D11 D10 GND E3 I/0-A13 E8 I/0-D13 E10 I/0-D15 F1 I/0-A15 F3 ...

Page 17

... XCR3064A: 64 Macrocell CPLD With Enhanced Clocking XCR3064A - 100-pin VQFP Package Pin # Function 1 I/O-A6 2 I/O- I/O-A8 (TDI I/O- I/O-A10 9 I/O-A11 10 I/O-A12 11 GND 12 I/O-A13 13 I/O-A14 14 I/O-A15 15 I/O-B15 (TMS) 16 I/O-B14 17 I/O-B13 I/O-B12 20 I/O-B11 21 I/O-B10 I/O- I/O-B8 26 GND ...

Page 18

... Revision History Date Version # 9/16/99 1.0 Initial Xilinx release. 2/7/00 1.1 Converted to Xilinx format and updated. DS037 (v1.1) February 10, 2000 XCR3064A: 64 Macrocell CPLD With Enhanced Clocking Temperature Range C = Commercial Industrial, T Packaging Options VQ44: 44-pin VQFP PC44: 44-pin PLCC CP56: 56-ball Chip Scale VQ100: 100-pin VQFP 44 ...

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