xcr3064a Xilinx Corp., xcr3064a Datasheet

xcr3064a

Manufacturer Part Number

xcr3064a

Description

64 Macrocell Cpld With Enhanced Clocking , Inc

Manufacturer

Xilinx Corp.

Datasheet

1.XCR3064A.pdf (18 pages)

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Download datasheet (198Kb)

DS037 (v1.1) February 10, 2000

Features

• Industry's first TotalCMOS™ PLD - both CMOS design

• Fast Zero Power (FZP™) design technique provides

• 3V, In-System Programmable (ISP) using a JTAG

• High speed pin-to-pin delays of 7.5 ns

• Ultra-low static power of less than 100 µ A

• 5V tolerant I/Os to support mixed Voltage systems

• 100% routable with 100% utilization while all pins and

• Deterministic timing model that is extremely simple to

• Up to 12 clocks with programmable polarity at every

• Support for complex asynchronous clocking

• Innovative XPLA™ architecture combines high speed

• 1000 erase/program cycles guaranteed

• 20 years data retention guaranteed

• Logic expandable to 37 product terms

• Advanced 0.35 µ E

• Security bit prevents unauthorized access

• Design entry and verification using industry standard

• Reprogrammable using industry standard device

• Innovative Control Term structure provides either sum

• Programmable global 3-state pin facilitates `bed of

• Available in PLCC, VQFP, and Chip Scale BGA

• Industrial grade operates from 2.7V to 3.6V

DS037 (v1.1) February 10, 2000

and process technologies

ultra-low power and very high speed

interface

- On-chip superVoltage generation

- ISP commands include: Enable, Erase, Program,

- Supported by multiple ISP programming platforms

- Four pin JTAG interface (TCK, TMS, TDI, TDO)

- JTAG commands include: Bypass, Idcode

all macrocells are fixed

use

macrocell

with extreme flexibility

and Xilinx CAE tools

programmers

terms or product terms in each logic block for:

- Programmable 3-state buffer

- Asynchronous macrocell register preset/reset

- Up to two asynchronous clocks

nails' testing without using logic resources

packages

Verify

CMOS process

APPLICATION NOTE

www.xilinx.com

1-800-255-7778

14*

XCR3064A: 64 Macrocell CPLD With

Enhanced Clocking

Product Specification

Description

The XCR3064A CPLD (Complex Programmable Logic

Device) is the second in a family of CoolRunner™ CPLDs

from Xilinx. These devices combine high speed and zero

power in a 64 macrocell CPLD. With the FZP design tech-

nique, the XCR3064A offers true pin-to-pin speeds of 7.5

ns, while simultaneously delivering power that is less than

100 µ A at standby without the need for "turbo bits" or other

power down schemes. By replacing conventional sense

amplifier methods for implementing product terms (a tech-

nique that has been used in PLDs since the bipolar era)

with a cascaded chain of pure CMOS gates, the dynamic

power is also substantially lower than any competing

CPLD. These devices are the first TotalCMOS PLDs, as

they use both a CMOS process technology and the pat-

ented full CMOS FZP design technique.

The Xilinx FZP CPLDs utilize the patented XPLA

(eXtended Programmable Logic Array) architecture. The

XPLA architecture combines the best features of both PLA

and PAL type structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA structure in

each logic block provides a fast 7.5 ns PAL path with five

dedicated product terms per output. This PAL path is joined

by an additional PLA structure that deploys a pool of 32

product terms to a fully programmable OR array that can

allocate the PLA product terms to any output in the logic

block. This combination allows logic to be allocated effi-

ciently throughout the logic block and supports as many as

37 product terms on an output. The speed with which logic

is allocated from the PLA array to an output is only 1.5 ns,

regardless of the number of PLA product terms used, which

results in worst case t

other pin. In addition, logic that is common to multiple out-

puts can be placed on a single PLA product term and

shared across multiple outputs via the OR array, effectively

increasing design density.

The XCR3064A CPLDs are supported by industry standard

CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor, Syn-

opsys, Synario, Viewlogic, and Synplicity), using text

(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-

ification uses industry standard simulators for functional

and timing simulation. Development is supported on per-

sonal computer, Sparc, and HP platforms. Device fitting

uses a Xilinx developed tool, XPLA Professional (available

on the Xilinx web site).

's of only 9.0 ns from any pin to any

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