XCR3128A-10TQ128C XILINX [Xilinx, Inc], XCR3128A-10TQ128C Datasheet
XCR3128A-10TQ128C
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XCR3128A-10TQ128C Summary of contents
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... Xilinx. These devices combine high speed and zero power in a 128 macrocell CPLD. With the FZP design tech- nique, the XCR3128A offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 µA at standby without the need for ‘turbo bits' or other power-down schemes ...
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... ZIA 36 36 LOGIC BLOCK LOGIC BLOCK www.xilinx.com 1-800-255-7778 of the XCR3128A device PD for the XCR3128A using six MC0 MC1 LOGIC I/O BLOCK MC15 MC0 MC1 LOGIC I/O BLOCK MC15 MC0 MC1 LOGIC I/O BLOCK MC15 MC0 MC1 LOGIC ...
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... XCR3128A: 128 Macrocell CPLD with Enhanced Clocking 36 ZIA INPUTS CONTROL 5 PAL ARRAY PLA ARRAY (32) Figure 2: Xilinx XPLA Logic Block Architecture 3 6 www.xilinx.com 1-800-255-7778 R SP00435A DS035 (v1.2) August 10, 2000 ...
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... R Macrocell Architecture Figure 3 shows the architecture of the macrocell used in the CoolRunner XCR3128A. The macrocell can be config- ured as either T-type flip-flop or a combinatorial logic function. A D-type flip-flop is generally more useful for implementing state machines and data buffering while a T-type flip-flop is generally more useful in implementing counters ...
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... XCR3128A: 128 Macrocell CPLD with Enhanced Clocking Simple Timing Model Figure 4 shows the CoolRunner Timing Model. The Cool- Runner timing model looks very much like a 22V10 timing model in that there are three main timing parameters, including and other competing architec- ...
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... Xilinx to offer CPLDs which are both high-performance and low power, breaking the para- digm that to have low power, you must have low perfor- mance. Refer to Frequency of the XCR3128A TotalCMOS CPLD (data taken with eight up/down, loadable 16-bit counters at 3.3V, 25°C). 20 ...
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... JTAG scan chain. The Xilinx XCR3128A’s JTAG interface includes a TAP Port defined by the IEEE 1149.1 JTAG Specification. As imple- mented in the Xilinx XCR3128A, the TAP Port includes four of the five pins (refer to Table 3) described in the JTAG specification: TCK, TMS, TDI, and TDO ...
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... A set of low-level ISP basic commands implemented in the XCR3128A enable this feature. The ISP commands imple- mented in the Xilinx XCR3128A are specified in Please note that an ENABLE command must precede all ISP commands unless an ENABLE command has already been given for a preceding ISP command ...
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... I/O pins. Note that an I/O macrocell used as buried logic that does not have the I/O pin used for input is considered to be unused, and the pull-down resistors will be turned on. We recommend that any unused I/O pins on the XCR3128A device be left unconnected. 9 Instruction Code 1001 Enables the Erase, Program, and Verify commands ...
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... Embedded Processor • Automated test equipment • Third party programmers • High-end ISP tools For more details on JTAG and ISP for the XCR3128A, refer to the related application note: JTAG and ISP Overview for Xilinx XPLA1 and XPLA2 CPLDs Parameter www.xilinx.com 1-800-255-7778 Min ...
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... XCR3128A: 128 Macrocell CPLD with Enhanced Clocking Absolute Maximum Ratings Symbol Supply voltage V Input voltage I V Output voltage OUT I Input current IN T Maximum junction temperature J T Storage temperature str Notes: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. ...
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... RP t Input to register reset RR Notes: 1. Specifications measured with one output switching. See 2. This parameter guaranteed by design and characterization, not by test. 3. Output pF. L DS035 (v1.2) August 10, 2000 XCR3128A: 128 Macrocell CPLD with Enhanced Clocking 1 For Commercial Grade Devices ≤ 3. Min. Max. 2 7.5 3 ...
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... XCR3128A: 128 Macrocell CPLD with Enhanced Clocking DC Electrical Characteristics For Industrial Grade Devices Industrial: -40°C ≤ T ≤ +85°C; 2.7V ≤ V AMB Symbol Parameter V Input voltage Low IL V Input voltage High IH V Input clamp voltage I V Output voltage Low OL V Output voltage High ...
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... RP t Input to register reset RR Notes: 1. Specifications measured with one output switching. See 2. This parameter guaranteed by design and characterization, not by test. 3. Output pF. L DS035 (v1.2) August 10, 2000 XCR3128A: 128 Macrocell CPLD with Enhanced Clocking 1 For Industrial Grade Devices ≤ 3.6V CC Parameter 2 1/( ...
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... XCR3128A: 128 Macrocell CPLD with Enhanced Clocking Switching Characteristics The test load circuit and load values for the AC Electrical Characteristics are illustrated below OUT 3.3V, 25°C DD 6.1 6.0 5.9 5.8 t 5.7 PD_PAL (ns) 5.6 5.5 5.4 5.3 5.2 5 NUMBER OF OUTPUTS SWITCHING Figure 6: t vs. Outputs Switching ...
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... R Pin Function and Laynout XCR3128A: 100-pin VQFP, and 128-pin TQFP Pin Function Table Function Pin Pin 100-pin 128-pin # # VQFP TQFP 1 I/O-A2 I/O- I/O-A0 I/O- I/O- I/O-B15 (TDI I/O-B13 I/O-B12 I/O-B10 I/O-B8 I/O-B15 (TDI I/O-B7 I/O-B13 41 10 I/O-B5 I/O-B12 42 11 ...
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... XCR3128A: 128 Macrocell CPLD with Enhanced Clocking 100-pin VQFP 100 76 1 VQFP TQFP Ordering Information Example: XCR3128A -7 VQ 100 C Device Type Speed Options Speed Options -15 pin-to-pin delay -12 pin-to-pin delay -10 pin-to-pin delay -7: 7.5 ns pin-to-pin delay ...