XCR3128A-10TQ128C XILINX [Xilinx, Inc], XCR3128A-10TQ128C Datasheet - Page 5

• Manufacturer Part Number: XCR3128A-10TQ128C
• Description: CPLD with Enhanced Clocking
• Manufacturer: XILINX [Xilinx, Inc]

XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
Simple Timing Model
Figure 4
Runner timing model looks very much like a 22V10 timing
model in that there are three main timing parameters,
including t
tures, the user may be able to fit the design into the CPLD,
but is not sure whether system timing requirements can be
met until after the design has been fit into the device. This is
Figure 4: CoolRunner Timing Model
5
shows the CoolRunner Timing Model. The Cool-
PD
GLOBAL CLOCK PIN
, t
SU
, and t
INPUT PIN
INPUT PIN
CO
. In other competing architec-
t
t
SU_PLA
SU_PAL
REGISTERED
= PAL ONLY
= PAL + PLA
t
t
PD_PLA
PD_PAL
www.xilinx.com
1-800-255-7778
= COMBINATORIAL PAL ONLY
= COMBINATORIAL PAL + PLA
D
because the timing models of competing architectures are
very complex and include such things as timing dependen-
cies on the number of parallel expanders borrowed, shar-
able expanders, varying number of X and Y routing
channels used, etc. In the XPLA architecture, the user
knows up front whether the design will meet system timing
requirements. This is due to the simplicity of the timing
model.
Q
REGISTERED
t
CO
DS035 (v1.2) August 10, 2000
OUTPUT PIN
OUTPUT PIN
SP00553
R