DSP56001FE33 MOTOROLA [Motorola, Inc], DSP56001FE33 Datasheet - Page 25

• Manufacturer Part Number: DSP56001FE33
• Description: 24-Bit General Purpose Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

DSP56001
Num
67
68
69
71
72
Clock Low Period
Clock High Period
Output Data Setup to Clock Rising
Edge (Internal Clock)
Output Data Hold After Clock Rising
Edge (Internal Clock)
Asynchronous Clock Cycle
(Vcc = 5.0 Vdc + 10%, T
Vcc = 5.0 Vdc + 5%, T
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
tACC = Asynchronous clock cycle time
tACC = Asynchronous Clock Cycle Time (for internal clock tACC is determined by the SCI clock control register and Icyc)
see SCI Figures 1 and 2)
Characteristics
DSP56001 Electrical Characteristics
AC Electrical Characteristics - SCI Timing
J
= -40 to +105° C, CL = 50 pf + 1 TTL Load at 33 MHz,
J
= -40 to +105° C, CL = 50 pf + 1 TTL Load at 20.5 MHz and 27 MHz,
SCI Asynchronous Mode Timing - 1X Clock
32
32
64
32
32
*
*
Min
-100
-100
cyc-20
cyc-20
*
*
*
cyc
cyc
cyc
20.5 MHz
Max
—
—
—
—
—
32
32
64
32
32
*
*
Min
cyc-15
cyc-15
-77
-77
*
*
*
cyc
cyc
cyc
27 MHz
Max
—
—
—
—
—
32
32
64
32
32
*
*
Min
cyc-13
cyc-13
-61
-61
*
*
*
cyc
cyc
cyc
33 MHz
Max
MOTOROLA
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
25