DSP56001FE33 MOTOROLA [Motorola, Inc], DSP56001FE33 Datasheet - Page 37

• Manufacturer Part Number: DSP56001FE33
• Description: 24-Bit General Purpose Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

DSP56001
Num
150
151
152
153
154
155
156
157
158
159
160
161
Clk Low Transition To BS Assertion
WT Assertion To Clk Low Transition
(setup time)
Clk Low Transition To WT Deassertion
For Minimum Timing
WT Deassertion To Clk Low Transition
For Maximum Timing (2 wait states
Clk High Transition To BS Deassertion
BS Assertion To Address Valid
BS Assertion To WT Assertion
(see Note 2)
BS Assertion To WT Deassertion
(See Note 2 and Note 4)
WT Deassertion To BS Deassertion
Minimum BS Deassertion Width For
Consecutive External Accesses
BS Deassertion To Address Invalid
(see Note 3)
Data-In Valid to RD Deassertion
(Set Up)
Note:
1.
2.
3.
4.
5.
Characteristics
AC timing specifications which are referenced to a device input signal are measured in production with
respect to the 50% point of the respective input signal’s transition.
If wait states are also inserted using the BCR and if the number of wait states is greater than 2, then
specification numbers 156 and 157 can be increased accordingly.
BS deassertion to address invalid indicates the time after which the address are no longer guaranteed
to be valid.
The minimum number of wait states when using BS/WT is two (2).
For read-modify-write instructions, the address lines will not change states between the read and the
write cycle. However, BS will deassert before asserting again for the write cycle. If wait states are de-
sired for each of the read and write cycle, the WT pin must be asserted once for each cycle.
AC Electrical Characteristics - Bus Strobe / Wait Timing
DSP56001 Electrical Characteristics
WS < 2
WS > 2
(WS-1)
cyc+tcl
tch-10
tch-7
Min
*
cyc
14
cyc
16
-2
4
4
8
5
0
20.5 MHz
2
2*cyc-15
WS*cyc
cyc-15
*
cyc-8
Max
cyc+tcl
+23
-15
24
26
10
—
—
—
—
(WS-1)
cyc+tcl
tch-6
tch-8
Min
*
cyc
11
cyc
12
-2
3
3
6
4
0
27 MHz
2
2*cyc-11
WS*cyc
cyc-11
*
cyc-6
Max
cyc+tcl
+17
-11
19
—
—
20
—
—
8
(WS-1)
*
cyc+tcl
tch-4.5
tch-6.5
cyc+4
cyc+4
Min
2.5
2.5
3.5
12
10
-2
5
0
33 MHz
2
2*cyc-10
WS*cyc
cyc-10
*
cyc-5
Max
cyc+tcl
MOTOROLA
+15
-10
6.5
19
19
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
37