ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet - Page 3

• Manufacturer Part Number: ADSP-TS202S_06
• Description: TigerSHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

GENERAL DESCRIPTION
The ADSP-TS202S TigerSHARC processor is an ultrahigh per-
formance, static superscalar processor optimized for large signal
processing tasks and communications infrastructure. The DSP
combines very wide memory widths with dual computation
blocks—supporting floating-point (IEEE 32-bit and extended
precision 40-bit) and fixed-point (8-, 16-, 32-, and 64-bit) pro-
cessing—to set a new standard of performance for digital signal
processors. The TigerSHARC static superscalar architecture lets
the DSP execute up to four instructions each cycle, performing
24 fixed-point (16-bit) operations or six floating-point
operations.
Four independent 128-bit wide internal data buses, each con-
necting to the six 2M bit memory banks, enable quad-word
data, instruction, and I/O accesses and provide 28G bytes per
second of internal memory bandwidth. Operating at 500 MHz,
the ADSP-TS202S processor’s core has a 2.0 ns instruction cycle
time. Using its single-instruction, multiple-data (SIMD) fea-
tures, the ADSP-TS202S processor can perform four billion
40-bit MACS or one billion 80-bit MACS per second.
shows the DSP’s performance benchmarks.
Table 1. General-Purpose Algorithm Benchmarks
at 500 MHz
1
The ADSP-TS202S processor is code-compatible with the other
TigerSHARC processors.
The Functional Block Diagram
TS202S processor’s architectural blocks. These blocks include
Benchmark
32-bit algorithm, 1 billion MACS/s peak performance
1K point complex FFT
64K point complex FFT
FIR filter (per real tap)
[8 × 8][8 × 8] matrix multiply (complex,
floating-point)
16-bit algorithm, 4 billion MACS/s peak performance
256 point complex FFT
I/O DMA transfer rate
External port
Link ports (each)
Cache preloaded.
• Dual compute blocks, each consisting of an ALU, multi-
• Dual integer ALUs (IALUs), each with its own 31-word
• A program sequencer with instruction alignment buffer
plier, 64-bit shifter, and 32-word register file and associated
data alignment buffers (DABs)
register file for data addressing and a status register
(IAB) and branch target buffer (BTB)
1
(Radix 2)
1
1
(Radix 2)
(Radix 2)
on Page 1
Speed
18.8 μs
2.8 ms
1 ns
2.8 μs
1.9 μs
1G bytes/s
1G bytes/s
shows the ADSP-
Rev. C | Page 3 of 48 | December 2006
Table 1
Clock
Cycles
9419
1397544
0.5
1399
928
n/a
n/a
Figure 2
SRAM and SDRAM.
processor system.
• An interrupt controller that supports hardware and soft-
• Four 128-bit internal data buses, each connecting to the six
• On-chip DRAM (12M-bit)
• An external port that provides the interface to host proces-
• A 14-channel DMA controller
• Four full-duplex LVDS link ports
• Two 64-bit interval timers and timer expired pin
• An 1149.1 IEEE compliant JTAG test access port for on-
Figure 2. ADSP-TS202S Single-Processor System with External SDRAM
REFERENCE
REFERENCE
CLK
ADDR
DATA
(OPTIONAL)
ware interrupts, supports level- or edge-triggers, and
supports prioritized, nested interrupts
2M-bit memory banks
sors, multiprocessing space (DSPs), off-chip memory-
mapped peripherals, and external SRAM and SDRAM
chip emulation
(OPTIONAL)
DEVICES
CLOCK
(4 MAX)
MEMORY
SDRAM
LINK
DQM
shows a typical single-processor system with external
RAS
CAS
CKE
A10
WE
CS
SCLK_V
LxDATI3–0P/N
LxCLKINP/N
SCLKRAT2–0
V
IRQ3–0
FLAG3–0
ID2–0
MSSD3–0
RAS
CAS
LDQM
HDQM
SDWE
SDCKE
SDA10
IOWR
IOEN
LxDATO3–0P/N
LxCLKOUTP/N
LxACKI
LxBCMPO
CONTROLIMP1–0
TMR0E
DS2–0
SCLK
IORD
LxACKO
LxBCMPI
RST_IN
RST_OUT
POR_IN
REF
ADSP-TS202S
Figure 4 on Page 8
REF
ADDR31–0
DATA63–0
BUSLOCK
WRH/WRL
DMAR3–0
BR7–0
MS1–0
BOFF
BRST
JTAG
BMS
CPA
DPA
MSH
HBR
HBG
ACK
BM
RD
shows a typical multi-
ADSP-TS202S
DATA
ADDR
DATA
ADDR
DATA
CS
ADDR
DATA
OE
WE
ACK
PROCESSOR
(OPTIONAL)
(OPTIONAL)
CS
DMA DEVICE
(OPTIONAL)
INTERFACE
(OPTIONAL)
MEMORY
EPROM
BOOT
HOST