ADSP-TS202S_06 AD [Analog Devices], ADSP-TS202S_06 Datasheet - Page 5

• Manufacturer Part Number: ADSP-TS202S_06
• Description: TigerSHARC Embedded Processor
• Manufacturer: AD [Analog Devices]

up a total of eight circular buffers. The IALUs handle address
pointer wraparound automatically, reducing overhead, increas-
ing performance, and simplifying implementation. Circular
buffers can start and end at any memory location.
Because the IALU’s computational pipeline is one cycle deep, in
most cases integer results are available in the next cycle. Hard-
ware (register dependency check) causes a stall if a result is
unavailable in a given cycle.
PROGRAM SEQUENCER
The ADSP-TS202S processor’s program sequencer supports the
following:
Interrupt Controller
The DSP supports nested and nonnested interrupts. Each inter-
rupt type has a register in the interrupt vector table. Also, each
has a bit in both the interrupt latch register and the interrupt
mask register. All interrupts are fixed as either level-sensitive or
edge-sensitive, except the IRQ3–0 hardware interrupts, which
are programmable.
The DSP distinguishes between hardware interrupts and soft-
ware exceptions, handling them differently. When a software
exception occurs, the DSP aborts all other instructions in the
instruction pipe. When a hardware interrupt occurs, the DSP
continues to execute instructions already in the instruction pipe.
Flexible Instruction Set
The 128-bit instruction line, which can contain up to four 32-bit
instructions, accommodates a variety of parallel operations for
concise programming. For example, one instruction line can
• A fully interruptible programming model with flexible pro-
• A 10-cycle instruction pipeline—four-cycle fetch pipe and
• Supply of instruction fetch memory addresses; the
• Management of program structures and program flow
• Branch prediction and a 128-entry branch target buffer
• Compact code without the requirement to align code in
gramming in assembly and C/C++ languages; handles
hardware interrupts with high throughput and no aborted
instruction cycles
six-cycle execution pipe—computation results available
two cycles after operands are available
sequencer’s instruction alignment buffer (IAB) caches up
to five fetched instruction lines waiting to execute; the pro-
gram sequencer extracts an instruction line from the IAB
and distributes it to the appropriate core component for
execution
determined according to JUMP, CALL, RTI, RTS instruc-
tions, loop structures, conditions, interrupts, and software
exceptions
(BTB) to reduce branch delays for efficient execution of
conditional and unconditional branch instructions and
zero-overhead looping; correctly predicted branches that
are taken occur with zero overhead cycles, overcoming the
five-to-nine stage branch penalty
memory; the IAB handles alignment
Rev. C | Page 5 of 48 | December 2006
direct the DSP to conditionally execute a multiply, an add, and a
subtract in both computation blocks while it also branches to
another location in the program. Some key features of the
instruction set include
DSP MEMORY
The DSP’s internal and external memory is organized into a
unified memory map, which defines the location (address) of all
elements in the system, as shown in
The memory map is divided into four memory areas—host
space, external memory, multiprocessor space, and internal
memory—and each memory space, except host memory, is sub-
divided into smaller memory spaces.
The ADSP-TS202S processor internal memory has 12M bits of
on-chip DRAM memory, divided into six blocks of 2M bits
(64K words × 32 bits). Each block—M0, M2, M4, M6, M8, and
M10—can store program instructions, data, or both, so applica-
tions can configure memory to suit specific needs. Placing
program instructions and data in different memory blocks,
however, enables the DSP to access data while performing an
instruction fetch. Each memory segment contains a 128K bit
cache to enable single-cycle accesses to internal DRAM.
The six internal memory blocks connect to the four 128-bit wide
internal buses through a crossbar connection, enabling the DSP
to perform four memory transfers in the same cycle. The DSP’s
internal bus architecture provides a total memory bandwidth of
28G bytes per second, enabling the core and I/O to access eight
32-bit data-words and four 32-bit instructions each cycle. The
DSP’s flexible memory structure enables
• Algebraic assembly language syntax
• Direct support for all DSP, imaging, and video arithmetic
• Eliminates toggling DSP hardware modes because modes
• Branch prediction encoded in instruction; enables zero-
• Parallelism encoded in instruction line
• Conditional execution optional for all instructions
• User-defined partitioning between program and data
• DSP core and I/O accesses to different memory blocks in
• DSP core access to three memory blocks in parallel—one
• Programmable partitioning of program and data memory
• Program access of all memory as 32-, 64-, or 128-bit
types
are supported as options (for example, rounding, satura-
tion, and others) within instructions
overhead loops
memory
the same cycle
instruction and two data accesses
words—16-bit words with the DAB
Figure
ADSP-TS202S
3.