AD14160KB-4 AD [Analog Devices], AD14160KB-4 Datasheet - Page 16

• Manufacturer Part Number: AD14160KB-4
• Description: Quad-SHARC DSP Multiprocessor Family
• Manufacturer: AD [Analog Devices]

AD14160/AD14160L
Parameter
Clock Input
Timing Requirements:
t
t
t
t
Parameter
Reset
Timing Requirements:
t
t
NOTES
1
2
Parameter
Interrupts
Timing Requirements:
t
t
t
NOTES
1
2
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is
Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
Only required for IRQx recognition in the following cycle.
Applies only if t
CK
CKL
CKH
CKRF
WRST
SRST
low, assuming stable V
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after
reset.
SIR
HIR
IPW
SIR
and t
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
RESET Pulsewidth Low
RESET Setup Before CLKIN High
IRQ
IRQ
IRQ
DD
HIR
and CLKIN (not including start-up time of external clock oscillator).
2-0
2-0
2-0
requirements are not met.
RESET
CLKIN
Setup Before CLKIN High
Hold Before CLKIN High
Pulsewidth
2
CLKIN
IRQ
CLKIN
2-0
1
1
2
1
Figure 9. Clock Input
Figure 11. Interrupts
Figure 10. Reset
Min
5
Min
4t
14.5 + DT/2 t
Min
18 + 3DT/4
2 + t
25
7
t
CK
CKH
t
IPW
40 MHz–5 V
40 MHz–5 V
40 MHz–5 V
CK
–16–
t
WRST
t
t
CK
SIR
Max
Max
Max
12 + 3DT/4
100
3
CK
t
t
HIR
CKL
t
SRST
Min
25
8.75
5
Min
4t
14.5 + DT/2 t
Min
18 + 3DT/4
2 + t
CK
40 MHz–3.3 V
40 MHz–3.3 V
40 MHz–3.3 V
CK
Max
100
3
Max
Max
12 + 3DT/4
CK
REV. A
Units
ns
ns
ns
ns
Units
ns
ns
Units
ns
ns
ns