AD14160KB-4 AD [Analog Devices], AD14160KB-4 Datasheet - Page 36

• Manufacturer Part Number: AD14160KB-4
• Description: Quad-SHARC DSP Multiprocessor Family
• Manufacturer: AD [Analog Devices]

AD14160/AD14160L
JTAG Test Access Port and Emulation
Parameter
Timing Requirements:
t
t
t
t
t
t
Switching Characteristics:
t
t
NOTES
1
2
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
System Inputs = DATA
TCLKy0, TCLKy1, RCLKy0, RCLKy1, TFSy0, TFSy1, RFSy0, RFSy1, LxDAT
System Outputs = DATA
DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low
System Inputs Hold After TCK Low
TRST Pulsewidth
TDO Delay from TCK Low
System Outputs Delay After TCK Low
47-0
47-0
OUTPUTS
, ADDR
SYSTEM
SYSTEM
INPUTS
, ADDR
TCK
TMS
TDO
TDI
31-0
31-0
, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR
, MS
3-0
, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR
Figure 25. IEEE 11499.1 JTAG Test Access Port
t
DTDO
1
1
2
t
t
STAP
DSYS
Min
t
5.5
6.5
8
18.5
4t
CK
–36–
CK
3-0
40 MHz–5 V
, LxCLK, LxACK, BMS.
3-0
, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.
t
t
TCK
HTAP
Max
13.5
20
t
SSYS
6-1
, RPBA, IDy2-0, IRQ
Min
t
5.5
6.5
8
19
4t
CK
CK
40 MHz–3.3 V
t
HSYS
6-1
, CPA, FLAG
2-0
, FLAGy3-0, DRy0, DyR1,
Max
13.5
20
2-0
, TIMEXP, DT0,
REV. A
ns
Units
ns
ns
ns
ns
ns
ns
ns