AD14160KB-4 AD [Analog Devices], AD14160KB-4 Datasheet - Page 31

• Manufacturer Part Number: AD14160KB-4
• Description: Quad-SHARC DSP Multiprocessor Family
• Manufacturer: AD [Analog Devices]

Link Ports: 2
Parameter
Receive
Timing Requirements:
t
t
t
t
t
Switching Characteristics:
t
t
Transmit
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
NOTE
1
REV. A
SLDCL
HLDCL
LCLKIW
LCLKRWL
LCLKRWH
DLAHC
DLALC
SLACH
HLACH
DLCLK
DLDCH
HLDCH
LCLKTWL
LCLKTWH
DLACLK
LACK will go low with t
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period (2
LCLK Width Low
LCLK Width High
LACK High Delay After CLKIN High
LACK Low Delay After LCLK High
LACK Setup Before LCLK High
LACK Hold After LCLK High
LCLK Delay After CLKIN
Data Delay After LCLK High
Data Hold After LCLK High
LCLK Width Low
LCLK Width High
LCLK Low Delay After LACK High
CLK Speed Operation
DLALC
relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
Operation)
1
Min
2.5
2.25
t
4.5
4.25
18 + DT/2
6
19
–6.75
–2
(t
(t
(t
CK
CK
CK
CK
/2
/4) – 1
/4) – 1
/4) + 9
40 MHz–5 V
–31–
Max
29 + DT/2
16.5
8.5
3
(t
(t
(3
CK
CK
/4) + 1
/4) + 1
t
CL
/4) + 17
Min
2.25
2.25
t
5
4
18 + DT/2
6
19
–6.5
–2
(t
(t
(t
CK
CK
CK
CK
/2
/4) – 0.75
/4) – 1.5
/4) + 9
40 MHz–3.3 V
AD14160/AD14160L
30 + DT/2
18.5
8.5
2.75
(t
(3
Max
(t
CK
CK
/4) + 1.5
/4) + 1
t
CL
/4) + 17
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns