AT40KEL040KW1-E ATMEL [ATMEL Corporation], AT40KEL040KW1-E Datasheet
AT40KEL040KW1-E
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AT40KEL040KW1-E Summary of contents
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Features • SRAM based FPGA Dedicated to Space Use • SEE Hardened Cells (configuration RAM, FreeRAM, DFF, JTAG, I/O buffers) Remove the need for Triple Modular Redundancy (TMR) • Produced on Rad Hard 0.35µm CMOS Process • Functionally and Pin ...
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Description Fast, Flexible and Efficient SRAM Fast, Efficient Array and Vector Multipliers Cache Logic Design Automatic Component Generators AT40KEL040 2 Table 1. AT40KEL040 *** Device Available ASIC Gates (50% typ. routable) Rows x Columns Core Cells Registers RAM Bits I/O ...
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AT40KEL040 Configurator 4155I–AERO–06/06 proven functions. The Automatic Component Generators work seamlessly with industry- standard schematic and synthesis tools to create the fastest, most efficient designs available. The patented AT40KEL040 series architecture employs a symmetrical grid of small yet powerful cells ...
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The Symmetrical Array AT40KEL040 4 At the heart of the Atmel architecture is a symmetrical array of identical cells (Figure 1). The array is continuous from one edge to the other, except for bus repeaters spaced every four cells (Figure ...
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RAM RAM RAM RAM RV RV 4155I–AERO–06/06 Figure 2. Floorplan (Representative Portion) = Core Cell RAM ...
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The Busing Network Table 2. Dual-function Buses Function Type Cell Output Enable Local RAM Output Enable Express RAM Write Enable Express RAM Address Express RAM Data In Local RAM Data Out Local Clocking Express Set/Reset Express AT40KEL040 6 Figure 3 ...
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Figure 3. Busing Plane (One of Five) 4155I–AERO–06/06 AT40KEL040 = AT40K/40KAL = Local/Local or Express/Express Turn Point = Row Repeater = Column Express Express bus bus Local bus 7 ...
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Cell Connections Figure 4. Cell Connections CEL CEL CEL CEL CEL CEL (a) Cell-to-cell Connections AT40KEL040 8 Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors. Figure 4(b) shows the connections between a cell and five ...
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The Cell Figure 5. The Cell "1" "1" N "1" 8X1 LUT 8X1 LUT OUT "0" "1" CLOCK RESET/SET 4155I–AERO–06/06 Figure 5 ...
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Figure 6. Some Single Cell Modes CARRY AT40KEL040 10 Synthesis Mode. This mode is particularly important ...
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RAM 4155I–AERO–06/ dual-ported RAM blocks are dispersed throughout the array as shown in Figure 7. A 4-bit Input Data Bus connects to four horizontal local buses distributed over four sec- tor rows (plane 1). A 4-bit Output ...
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Figure 8. RAM Logic “1” Ain 5 Aout WEN 4 Din AT40KEL040 12 data flows through the bit. When a nibble is not (Write) addressed or LOAD is logic logic 1, data is ...
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Figure 9. RAM Example: 128 x 8 Dual-ported RAM (Asynchronous) 4155I–AERO–06/06 13 ...
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Clocking Scheme AT40KEL040 14 There are eight Global Clock buses (GCK1 - GCK8) on the AT40KEL040 FPGA. Each of the eight dedicated Global Clock buses is connected to one of the dual-use Global Clock pins. Any clocks used in the ...
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Figure 10. Clocking (for One Column of Cells) Express Bus (Plane 4; Half length at edge) 4155I–AERO–06/06 “1” Sector Clock Mux Global Clock Line (Buried) “1” Repeater Sector Clock Mux “1” “1” FCK (2 per Edge Column of the Array) ...
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Set/Reset Scheme AT40KEL040 16 The AT40KEL040 family reset scheme is essentially the same as the clock scheme except that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by any User I/O, except those used ...
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Figure 11. Set/Reset (for One Column of Cells) Repeater Express Bus (Plane 5; Half length at edge) 4155I–AERO–06/06 Each Cell has a programmable Set or Reset Sector Set/Reset Mux “1” Global Set/Reset Line (Buried) “1” “1” “1” Any User I/O ...
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I/O Structure Pad Pull-up/Pull-down CMOS Schmitt Delays Drive Tri-State Source Selection Mux Primary, Secondary and Corner I/Os Primary I/O Secondary I/O AT40KEL040 18 AT40K has registered I/Os and group enable every sector for tri-states on obuf’s. The I/O pad is ...
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Corner I/O 4155I–AERO–06/06 connects on the diagonal inputs to the cell above and the cell below. It also connects to the repeater of the cell above and below. In addition, each Secondary I/O also connects into the busing network of ...
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Figure 12. South I/O (Mirrored for North I/O) AT40KEL040 20 (a) Primary I/O (a) Primary I/O (b) Secondary I/O 4155I–AERO–06/06 ...
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Figure 13. West I/O (Mirrored for East I/O) PULL-UP PAD PULL-DOWN 4155I–AERO–06/06 a. Primary I/0 "0" "1" "0" "1" b. Secondary I/O CELL CELL 21 ...
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Figure 14. Northwest Corner I/O (Similar NE/SE/SW Corners) VCC DRIVE TRI-ST ATE RST PULL-UP PAD PULL-DOWN AT40KEL040 22 PAD VCC GND DRIVE TTL/CMOS TRI-ST ATE SCHMITT DELAY ICLK OCLK RST RST "0" "1" "0" "1" PAD GND TTL/CMOS SCHMITT DELAY ...
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Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125 °C Storage Temperature ..................................... -65°C to +150°C Junction Temperature .................................................. +150°C Voltage on Any Input Pin (1) with Respect to Ground ......-0.5V to 5.5V DC (KEL version) ................................................ -0.5V to ...
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DC Characteristics Symbol Parameter V High-level Input Voltage IH V Low-level Input Voltage IL V High-level Output Voltage OH V Low-level Output Voltage OL I High-level Input Current IH I Low-level Input Current IL High-level Tri-state Output I OZH Leakage ...
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AC Timing Characteristics Delays are based on fixed loads which are described in the notes. Maximum timing based on worst case: V Minimum timing based on best case: V Maximum delays are the average of t Cell Function Parameter Core ...
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Cell Function Parameter I/O Input t PD Input t PD Input t PD Input t PD Output, slow t PD Output, medium t PD Output, fast t PD Output, slow t PZX Output, slow t PXZ Output, medium t PZX ...
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AC Timing Characteristics Clocks and Reset Input buffers are measured from a V Maximum timings for clock input buffers and internal drivers are measured for rising edge delays only. Cell Function Parameter Global Clocks and Set/Reset GCK Input buffer t ...
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AC Timing Characteristics Cell Function Parameter Asynchronous RAM Write t (min) WECYC Write t (min) WEL Write t (min) WEH Write t (min) setup Write t (min) hold Write t (min) setup Write t (min) hold Write t (min) hold ...
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FreeRAM Asynchronous Timing Characteristics Single Port Write/Read Dual Port Write with Read Dual Port Read 4155I–AERO–06/06 29 ...
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FreeRAM Synchronous Timing Characteristics Single Port Write/Read CLK WE ADDR OE DATA Dual Port Write with Read CLK WE WR ADDR WR DATA RD ADDR = WR ADDR 1 RD DATA AT40KEL040 30 t CLKH t t WCS WCH t ...
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Dual Port Read RD ADDR OE DATA 4155I–AERO–06/ OZX OXZ 31 ...
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Table 4. MQFP F-160 Pin Number AT40KEL040 ...
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Pin Number 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 AT40KEL040 33 Pin Signal ...
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Table 5. MQFP - F256 Pin Number ...
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Pin Number 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 AT40KEL040 35 Pin Signal ...
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Pin Number 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 AT40KEL040 36 Pin Signal ...
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Part/Package Availability and User I/O Counts (Including Dual-function Pins) 4155I–AERO–06/06 Package MQFPF 160 MQFPF 256 AT40KEL040 129 233 37 ...
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... Ordering Information Part Number AT40KEL040KW1-E 5962-0325001QXC 5962-0325001VXC 930400801 AT40KEL040KZ1-E 5962-0325001QYC 5962-0325001VYC 930400802 AT40KFL040KW1-E 5962-0325002QXC 5962-0325002VXC AT40KFL040KW1-SCC AT40KFL040KZ1-E 5962-0325002QYC 5962-0325002VYC AT40KFL040KZ1-SCC AT40KEL040 38 Package Version MQFPF160 3.3V MQFPF160 3.3V MQFPF160 3.3V MQFPF160 3.3V MQFPF256 3.3V MQFPF256 3.3V MQFPF256 3.3V MQFPF256 3.3V MQFPF160 3.3V, 5V Tolerant MQFPF160 3.3V, 5V Tolerant MQFPF160 3.3V, 5V Tolerant MQFPF160 3.3V, 5V Tolerant MQFPF256 3.3V, 5V Tolerant MQFPF256 3 ...
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Package Drawing Multilayer Quad Flat Pack (MQFP) 160-pin - Front View 4155I–AERO–06/06 39 ...
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Multilayer Quad Flat Pack (MQFP) 256-pin - Front View AT40KEL040 40 4155I–AERO–06/06 ...
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Datasheet Change Log Changes from 4155B - 06/03 to 4155C 04/04 Changes from 4155C - 06/03 to 4155D 04/04 Changes from 4155D 04/ 4155E 06/04 Changes from 4155E 06/04 to 4155F 06/04 Changes from 4155F 06/04 to 4155G ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...