AT40KEL040KW1-E ATMEL [ATMEL Corporation], AT40KEL040KW1-E Datasheet - Page 19
AT40KEL040KW1-E
Manufacturer Part Number
AT40KEL040KW1-E
Description
Rad Hard Reprogrammable FPGAs with FreeRAM
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT40KEL040KW1-E.pdf
(42 pages)
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Corner I/O
4155I–AERO–06/06
connects on the diagonal inputs to the cell above and the cell below. It also connects to
the repeater of the cell above and below. In addition, each Secondary I/O also connects
into the busing network of the two nearest edge cells. This is an extremely powerful fea-
ture, as it provides logic cells toward the center of the array with fast access to I/Os via
local and express buses. It can be seen from the diagram that a given Secondary I/O
can be accessed from any logic cell on two rows or columns of the FPGA. See Figure
12a and Figure 13b.
Logic cells at the corner of the FPGA array have direct-connect access to five separate
I/Os: 2 Primary, 2 Secondary and 1 Corner I/O. Corner I/Os are like an extra Secondary
I/O at each corner of the array. With the inclusion of Corner I/Os, an AT40KEL040
FPGA with n x n core cells always has 8n I/Os. As the diagram shows, Corner I/Os can
be accessed both from the corner logic cell and the horizontal and vertical busing net-
works running along the edges of the array. This means that many different edge logic
cells can access the Corner I/Os. See Figure 14.
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