XC4VFX12 XILINX [Xilinx, Inc], XC4VFX12 Datasheet - Page 2

• Manufacturer Part Number: XC4VFX12
• Manufacturer: XILINX [Xilinx, Inc]

Virtex-4 Family Overview
Table 1: Virtex-4 FPGA Family Members (Continued)
Notes:
1.
2.
500 MHz Xesium Clock Technology
•
•
•
•
•
Flexible Logic Resources
•
•
•
22
XC4VSX25
XC4VSX35
XC4VSX55
XC4VFX12
XC4VFX20
XC4VFX40
XC4VFX60
XC4VFX100
XC4VFX140
Device
One CLB = Four Slices = Maximum of 64 bits.
Each XtremeDSP slice contains one 18 x 18 multiplier, an adder, and an accumulator
Up to twenty Digital Clock Manager (DCM) modules
-
-
-
-
-
-
-
-
-
Companion Phase-Matched Clock Divider (PMCD)
blocks
Differential clocking structure for optimized low-jitter
clocking and precise duty cycle
32 Global Clock networks
Regional I/O and Local clocks
Up to 40% speed improvement over previous
generation devices
Up to 200,000 logic cells including:
-
-
-
Cascadable variable shift registers or distributed
memory capability
Precision clock deskew and phase shift
Flexible frequency synthesis
Dual operating modes to ease performance
trade-off decisions
Improved maximum input/output frequency
Improved phase shifting resolution
Reduced output jitter
Low-power operation
Enhanced phase detectors
Wide phase shift range
Up to 178,176 internal registers with clock enable
(XC4VLX200)
Up to 178,176 look-up tables (LUTs)
Logic expanding multiplexers and I/O registers
Row x Col
128 x 48
128 x 52
160 x 68
192 x 84
64 x 40
96 x 40
64 x 24
64 x 36
96 x 44
Array
Configurable Logic Blocks (CLBs)
142,128
23,040
34,560
55,296
12,312
19,224
41,904
56,880
94,896
Logic
Cells
10,240
15,360
24,576
15,552
25,280
42,176
63,168
Slices
5,472
8,544
Distributed
RAM (Kb)
Max
160
240
384
134
243
395
659
987
86
(1)
Slices
Xtreme
DSP
128
192
512
128
160
192
32
32
48
(2)
Blocks
18 Kb
128
192
320
144
232
376
552
36
68
Block RAM
www.xilinx.com
RAM (Kb)
Block
2,304
3,456
5,760
1,224
2,592
4,176
6,768
9,936
Max
648
500 MHz XtremeDSP Slices
•
•
•
•
•
•
500 MHz Integrated Block Memory
•
•
•
•
•
•
•
•
•
•
DCMs PMCDs
12
12
20
4
8
8
4
4
8
Dedicated 18-bit x 18-bit multiplier,
multiply-accumulator, or multiply-adder blocks
Optional pipeline stages for enhanced performance
Optional 48-bit accumulator for multiply accumulate
(MACC) operation
Integrated adder for complex-multiply or multiply-add
operation
Cascadeable Multiply or MACC
Up to 100% speed improvement over previous
generation devices.
Up to 10Mb of integrated block memory
Optional pipeline stages for higher performance
Multi-rate FIFO support logic
-
-
-
Dual-port architecture
Independent read and write port width selection (RAM
only)
18 Kbit blocks (memory and parity/sideband memory
support)
Configurations from 16K x 1 to 512 x 36
(4K x 4 to 512 x 36 for FIFO operation)
Byte-write capability (connection to PPC405, etc.)
Dedicated cascade routing to form 32K x 1 memory
without using FPGA routing
Up to 100% speed improvement over previous
generation devices.
0
4
4
0
0
4
8
8
8
Full and Empty Flag support
Fully programmable AF and AE Flags
Synchronous/ Asynchronous Operation
Monitors
System
0
1
1
0
0
1
1
1
1
Blocks
ADC
0
0
0
0
0
0
1
1
1
Processor
PowerPC
Blocks
N/A
N/A
N/A
DS112 (v1.1) September 10, 2004
1
1
2
2
2
2
Advance Product Specification
Ethernet
MACs
N/A
N/A
N/A
2
2
4
4
4
4
Transciever
RocketIO
Blocks
N/A
N/A
N/A
N/A
12
16
20
24
8
Banks
Total
I/O
11
13
11
13
15
17
9
9
9
User
Max
320
448
640
320
320
448
576
768
896
I/O
R