XC4VFX12 XILINX [Xilinx, Inc], XC4VFX12 Datasheet - Page 4

• Manufacturer Part Number: XC4VFX12
• Manufacturer: XILINX [Xilinx, Inc]

Virtex-4 Family Overview
Tri-mode Ethernet Media Access Controller
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Architectural Description
Virtex-4 Array Overview
Virtex-4 devices are user-programmable gate arrays with
various configurable elements and embedded cores opti-
mized for high-density and high-performance system
designs. Virtex-4 devices implement the following function-
ality:
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IEEE 802.3 compliant
Operates at 10, 100, and 1,000 Mb/s
Supports tri-mode auto-detect
Receive address filter (16 address entries)
Fully monolithic 1000Base-X solution with RocketIO
MGT
Implements SGMII through RocketIO MGT to external
PHY device
I/O blocks provide the interface between package pins
and the internal configurable logic. Most popular and
leading-edge I/O standards are supported by
programmable I/O blocks (IOBs). The IOBs are
enhanced for source-synchronous applications.
Source-synchronous optimizations include per-bit
deskew, data serializer/deserializer, clock dividers, and
dedicated local clocking resources.
Configurable Logic Blocks (CLBs), the basic logic
elements for Xilinx FPGAs, provide combinatorial and
synchronous logic as well as distributed memory and
SRL16 shift register capability.
Block RAM modules provide flexible 18Kbit true
dual-port RAM, that are cascadable to form larger
memory blocks. In addition, Virtex-4 block RAMs
contain optional programmable FIFO logic for
increased device utilization.
Cascadable embedded XtremeDSP slices with 18-bit x
18-bit dedicated multipliers, integrated Adder, and
48-bit accumulator.
Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock
multiplication/division, and coarse-/fine-grained clock
phase shifting.
www.xilinx.com
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Additionally, FX devices support the following embedded
system functionality:
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The general routing matrix (GRM) provides an array of rout-
ing switches between each component. Each programma-
ble element is tied to a switch matrix, allowing multiple
connections to the general routing matrix. The overall pro-
grammable interconnection is hierarchical and designed to
support high-speed designs.
All
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
Supports multiple PHY (MII, GMII, etc.) interfaces
through an I/O resource
Receive and transmit statistics available through
separate interfaces
Separate host and client interfaces
Support for jumbo frames
Flexible, user-configurable host interface
System Monitor
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10-bit, 200 kSPS analog-to-digital converter in larger
devices.
Integrated high-speed serial transceivers enable data
rates up to 11.1 Gb/s per channel.
Embedded IBM PowerPC 405 RISC CPU (up to
450 MHz) with the auxiliary processor unit interface
10/100/1000 Ethernet media-access control (EMAC)
cores.
programmable
Differential analog channels plus on-chip
temperature and supply voltage monitors
Dedicated analog-only chip input channel is
provided for precision off-chip monitoring
Allows monitoring of on-chip or off-chip voltages
and temperatures
Alarm and peak detect functionality
elements,
DS112 (v1.1) September 10, 2004
Advance Product Specification
including
the
routing
R