XC3042 XILINX [Xilinx, Inc], XC3042 Datasheet - Page 39

• Manufacturer Part Number: XC3042
• Description: Logic Cell Array Families
• Manufacturer: XILINX [Xilinx, Inc]

Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed
outputs are default slew-rate limited.
This table describes the pinouts of three different chips in three different packages. The pin-description column lists 84 of the 118
pads on the XC3042 (and 84 of the 98 pads on the XC3030) that are connected to the 84 package pins. Ten pads, indicated by an
asterisk, do not exist on the XC3020, which has 74 pads; therefore the corresponding pins on the 84-pin packages have no
connections to an XC3020. Six pads on the XC3020 and 16 pads on the XC3030, indicated by a dash (—) in the 68 PLCC column,
have no connection to the 68 PLCC, but are connected to the 84-pin packages.
XC3030
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
—
—
—
—
—
—
—
—
68 PLCC
XC3020
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
—
—
—
—
—
XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts
XC3000 Families 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts
XC3030, XC3042
XTL2(IN)-I/O
TCLKIN-I/O
M1-RDATA
M0-RTRIG
PWRDN
HDC-I/O
XC3020
LDC-I/O
INIT-I/O
M2-I/O
VCC
GND
I/O*
I/O
I/O*
I/O*
I/O*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
*
84 PLCC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
84 PGA
L10
L11
G3
G1
G2
B2
C2
B1
C1
D2
D1
E3
E2
E1
F2
F3
F1
H1
H2
K1
K2
K3
K4
K5
K6
K7
K8
K9
J1
J2
L1
L2
L3
L4
J5
L5
J6
J7
L7
L6
L8
L9
2-141
68 PLCC
XC3030
XC3020
44
45
46
47
48
—
49
50
51
—
52
53
54
55
—
—
56
57
58
59
60
61
62
63
64
—
—
65
66
67
68
—
—
1
2
3
4
5
6
7
8
9
XTL1(OUT)-BCLKIN-I/O
RDY/BUSY-RCLK-I/O
XC3030, XC3042
A1-CS2-I/O
D0-DIN-I/O
A0-WS-I/O
DONE-PG
DOUT-I/O
XC3020
CS0-I/O
CS1-I/O
RESET
A15-I/O
A14-I/O
A13-I/O
A12-I/O
A11-I/O
A10-I/O
D7-I/O
D6-I/O
D5-I/O
D4-I/O
D3-I/O
D2-I/O
D1-I/O
A2-I/O
A3-I/O
A4-I/O
A5-I/O
A6-I/O
A7-I/O
A8-I/O
A9-I/O
CCLK
VCC
GND
I/O*
I/O*
I/O*
I/O*
I/O*
I/O
I/O
I/O
84 PLCC
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
10
11
1
2
3
4
5
6
7
8
9
84 PGA
H11
G10
G11
D11
K10
K11
H10
F10
F11
E11
E10
D10
C11
B11
C10
A11
B10
A10
J10
J11
G9
F9
E9
B9
A9
B8
A8
B6
B7
A7
C7
C6
A6
A5
B5
C5
A4
B4
A3
A2
B3
A1