XC5204 XILINX [Xilinx, Inc], XC5204 Datasheet - Page 35

• Manufacturer Part Number: XC5204
• Description: Field Programmable Gate Arrays
• Manufacturer: XILINX [Xilinx, Inc]

.
Note:
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Figure 32: Master Parallel Mode Programming Switching Characteristics
November 5, 1998 (Version 5.2)
(output)
(output)
(output)
(output)
A0-A17
D0-D7
DOUT
RCLK
CCLK
CCLK
1. At power-up, V
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
Low until V
R
CC
Delay to Address valid
Data setup time
Data hold time
is Valid.
CC
must rise from 2.0 V to V
Description
CC
min in less then 25 ms, otherwise delay configuration by pulling PROGRAM
Address for Byte n
1
2
3
Symbol
XC5200 Series Field Programmable Gate Arrays
7 CCLKs
T
T
T
DRC
RCD
RAC
2 T
Byte
DRC
Min
60
0
0
Byte n - 1
D6
Address for Byte n + 1
1 T
3 T
CCLK
RAC
RCD
Max
200
D7
Units
ns
ns
ns
X6078
7-117
7