XC5204 XILINX [Xilinx, Inc], XC5204 Datasheet - Page 37

• Manufacturer Part Number: XC5204
• Description: Field Programmable Gate Arrays
• Manufacturer: XILINX [Xilinx, Inc]

Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
Figure 34: Synchronous Peripheral Mode Programming Switching Characteristics
November 5, 1998 (Version 5.2)
CCLK
INIT
CCLK
2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation does
3. The pin name RDY/BUSY is a misnomer. In synchronous peripheral mode this is really an ACKNOWLEDGE signal.
4.Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,
first data byte on the second rising edge of CCLK after INIT goes high. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
not require such a response.
additional CCLK pulses are clearly required after the last byte has been loaded.
RDY/BUSY
1
T
R
IC
DOUT
D0 - D7
INIT (High) setup time
D0 - D7 setup time
D0 - D7 hold time
CCLK High time
CCLK Low time
CCLK Frequency
Description
T
CCL
BYTE
0
0
1
2
3
1
Symbol
XC5200 Series Field Programmable Gate Arrays
T
T
2
T
T
F
T
CCH
CCL
DC
CD
CC
IC
BYTE 0 OUT
3
4
Min
60
50
60
5
0
2
T
DC
5
BYTE
1
6
Max
8
7
3
T
CD
BYTE 1 OUT
0
Units
MHz
1
ns
ns
ns
ns
s
X6096
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7