MK60DN256ZVMD10 FREESCALE [Freescale Semiconductor, Inc], MK60DN256ZVMD10 Datasheet - Page 57
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MK60DN256ZVMD10
Manufacturer Part Number
MK60DN256ZVMD10
Description
K60 Sub-Family Data Sheet
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MK60DN256ZVMD10.pdf
(79 pages)
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6.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.8.1.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Freescale Semiconductor, Inc.
Symbol
MII1
MII2
MII3
MII4
MII5
MII6
MII7
MII8
—
—
RXCLK frequency
RXCLK pulse width high
RXCLK pulse width low
RXD[3:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[3:0], RXDV, RXER hold
TXCLK frequency
TXCLK pulse width high
TXCLK pulse width low
TXCLK to TXD[3:0], TXEN, TXER invalid
TXCLK to TXD[3:0], TXEN, TXER valid
Description
TXCLK (input)
TXD[n:0]
TXEN
TXER
K60 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Figure 20. MII transmit signal timing diagram
Table 38. MII signal switching specifications
MII8
MII6
Valid data
Valid data
Valid data
MII5
MII7
Peripheral operating requirements and behaviors
35%
35%
35%
35%
Min.
—
—
—
5
5
2
Max.
65%
65%
65%
65%
25
25
25
—
—
—
RXCLK
RXCLK
TXCLK
TXCLK
period
period
period
period
MHz
MHz
Unit
ns
ns
ns
ns
57
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