MK60DN256ZVMD10 FREESCALE [Freescale Semiconductor, Inc], MK60DN256ZVMD10 Datasheet - Page 64
MK60DN256ZVMD10
Manufacturer Part Number
MK60DN256ZVMD10
Description
K60 Sub-Family Data Sheet
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MK60DN256ZVMD10.pdf
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Peripheral operating requirements and behaviors
6.8.11 I
This section provides the AC timings for the I
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
64
Num
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
2
S switching specifications
Symbol
t
t
f
t
t
t
t
fpp
fpp
fpp
TLH
THL
t
OD
WL
WH
OD
ISU
IH
Table 46. SDHC switching specifications
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
Clock frequency (low speed)
Clock frequency (SD\SDIO full speed)
Clock frequency (MMC full speed)
Clock frequency (identification mode)
Clock low time
Clock high time
Clock rise time
Clock fall time
SDHC output delay (output valid)
SDHC input setup time
SDHC input hold time
Description
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
K60 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
SD3
SD6
(continued)
Figure 26. SDHC timing
SD2
SD7
2
S in master (clocks driven) and slave
SD8
SD1
Min.
—
—
-5
0
0
0
0
7
7
5
0
Freescale Semiconductor, Inc.
Max.
400
400
6.5
25
20
—
—
—
—
3
3
MHz
MHz
Unit
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
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