MK61FN1M0VMJ12 FREESCALE [Freescale Semiconductor, Inc], MK61FN1M0VMJ12 Datasheet - Page 48

• Manufacturer Part Number: MK61FN1M0VMJ12
• Description: K61 Sub-Family
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Peripheral operating requirements and behaviors
6.4.5 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
2. Specification is valid for all FB_AD[31:0] and FB_TA.
48
and FB_TS.
Num
Num
FB1
FB2
FB3
FB4
FB5
FB1
FB2
FB3
Operating voltage
Frequency of operation
Clock period
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
Operating voltage
Frequency of operation
Clock period
Address, data, and control output valid
Address, data, and control output hold
Description
Description
Table 27. Flexbus limited voltage range switching specifications
Table 28. Flexbus full voltage range switching specifications
Figure 19. DDR read timing, DQ vs. DQS
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
Table continues on the next page...
1/FB_CLK
1.71
Min.
Min.
2.7
0.5
8.5
0.5
20
—
—
—
—
0
FB_CLK
FB_CLK
Max.
11.5
Max.
13.5
3.6
3.6
—
—
—
—
—
—
Freescale Semiconductor, Inc.
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
V
Notes
Notes
1
1
2
2
1
1