MK61FN1M0VMJ12 FREESCALE [Freescale Semiconductor, Inc], MK61FN1M0VMJ12 Datasheet - Page 72

• Manufacturer Part Number: MK61FN1M0VMJ12
• Description: K61 Sub-Family
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Peripheral operating requirements and behaviors
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
72
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
range the maximum frequency of operation is reduced.
Num
DS2
DS3
DS4
DS5
DS6
DS7
DS8
DS10
DS11
DS12
DS13
DS14
DS15
DS16
Num
DS9
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DSPI_SCK to DSPI_PCSn invalid delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Table 47. Master mode DSPI timing (full voltage range) (continued)
Operating voltage
Frequency of operation
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Table 48. Slave mode DSPI timing (full voltage range)
Figure 34. DSPI classic SPI timing — master mode
DS7
DS3
Description
K61 Sub-Family Data Sheet, Rev. 4, 10/2012.
First data
Description
DS8
First data
DS5
DS2
Data
Data
DS6
(t
(t
(t
BUS
BUS
SCK
DS1
Last data
20.5
Min.
-4.5
—
/2) - 4
4
4
0
x 2) −
x 2) −
Last data
(t
SCK
8 x t
1.71
Min.
—
—
—
—
(t
0
2
7
/2) - 4
DS4
SCK/2)
BUS
Max.
10
—
—
—
—
—
+ 4
Freescale Semiconductor, Inc.
(t
SCK/2)
Max.
3.6
7.5
20
19
19
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
+ 4
MHz
Notes
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
2
3