MM908E621_08 FREESCALE [Freescale Semiconductor, Inc], MM908E621_08 Datasheet - Page 30

• Manufacturer Part Number: MM908E621_08
• Description: Integrated Quad Half-bridge and Triple High Side with Embedded MCU and LIN for High End Mirror
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

INTERRUPT MASK REGISTER (IMR)
L0IE - L0 Input Interrupt Enable Bit
L0IF. Reset clears the L0IE bit.
H0IE - H0 Input Interrupt Enable Bit
flag, H0IF. Reset clears the H0IE bit.
LINIE - LIN line Interrupt Enable Bit
LINIF. Reset clears the LINIE bit.
HTRD - High Temperature Reset Disable Bit
function. Reset clears the HTRD bit.
30
908E621
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Reset
Read
Write
This read/write bit enables CPU interrupts by the L0 flag,
This read/write bit enables CPU interrupts by the Hallport
This read/write bit enables CPU interrupts by the LIN flag,
This read/write bit disables the high temperature reset
1 = interrupt requests from L0IF flag enabled
0 = interrupt requests from L0IF flag disabled
1 = interrupt requests from H0IF flag enabled
0 = interrupt requests from H0IF flag disabled
1 = interrupt requests from LINIF flag enabled
0 = interrupt requests from LINIF flag disabled
1 = high temperature reset is disabled
0 = high temperature reset is enabled
Bit7
L0IE
0
Register Name and Address: IMR - $09
H0IE
6
0
LINIE
5
0
HTRD
4
0
HTIE
3
0
LVIE
2
0
HVIE
1
0
PSFIE
Bit0
0
a destruction of the part in cases of high temperature. This bit
was foreseen for test purposes only!
HTIE - High Temperature Interrupt Enable Bit
temperature flag, HTIF. Reset clears the HTIE bit.
LVIE - Low Voltage Interrupt Enable Bit
voltage flag, LVIF.Reset clears the LVIE bit.
HVIE - High Voltage Interrupt Enable Bit
voltage flag, HVIF.Reset clears the HVIE bit.
PSFIE - Power Stage Fail Interrupt Enable Bit
fail flag, PSFIF. Reset clears the PSFIE bit.
RESETS
source.
(1.25ms typical), after the reset event is gone.
Note: Disabling of the high temperature reset can lead to
This read/write bit enables CPU interrupts by the high
This read/write bit enables CPU interrupts by the low
This read/write bit enables CPU interrupts by the high
This read/write bit enables CPU interrupts by power stage
The 908E621 has four internal and one external reset
Each internal reset event will cause a reset pin low for t
1 = interrupt requests from HTIF flag enabled
0 = interrupt requests from HTIF flag disabled
1 = interrupt requests from LVIF flag enabled
0 = interrupt requests from LVIF flag disabled
1 = interrupt requests from HVIF flag enabled
0 = interrupt requests from HVIF flag disabled
1 = interrupt requests from PSFIF flag enabled
0 = interrupt requests from PSFIF flag disabled
Analog Integrated Circuit Device Data
Freescale Semiconductor
RST