MM908E621_08 FREESCALE [Freescale Semiconductor, Inc], MM908E621_08 Datasheet - Page 45

• Manufacturer Part Number: MM908E621_08
• Description: Integrated Quad Half-bridge and Triple High Side with Embedded MCU and LIN for High End Mirror
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

programming via the LIN, and are not intended for use in the
application.
System Status Register (SYSSTAT)
LINCL — LIN Current Limitation Bit
current limitation region. Due to excessive power dissipation
in the transmitter, the driver will be automatically turned off
after a certain time.
HTIF— Over-temperature Status Bit
Flag register
VF — Voltage Failure Bit
of the allowed range. The bit is set if either the LVIF or the
HVIF in the Interrupt Flag register is set.
H0F — H0 Failure Bit
Status and Control Register (HLSCTL)
Analog Integrated Circuit Device Data
Freescale Semiconductor
Reset
Read
Write
The high speed slew rates are used, for example, for
This read only bit is set if the LIN transmitter operates in
This read only bit is a copy of the HTIF bit in the Interrupt
This read only bit indicates that the supply voltage was out
This read only bit is a copy of the H0OCF bit in the H0/L0
SRS1
0
0
1
1
1 = transmitter operating in current limitation region
0 = transmitter not operating in current limitation region
1 = over-temperature condition
0 = no over-temperature condition
1 = low/high voltage condition detected
0 = no voltage failure condition detected
1 = over-current detected on H0
0 = no over-current on H0
LINC
Register Name and Address: SYSSTAT - $0C
Bit7
Table 10. LIN Slew Rate Selection Bits
L
0
SRS0
Figure 25. VF Flag Generation
HTIF
HVIF
LVIF
0
1
0
1
6
0
VF
5
0
H0F
Initial Slew Rate (20kBaud)
Slow Slew Rate (10kBaud)
4
0
High Speed II (8x)
High Speed I (4x)
HVD
DF
Slew rate
3
0
VF
HSF
2
0
HBF
1
0
Bit0
0
0
HVDDF— HVDD Failure Bit
Side Status register
HSF— HS1:3 Failure Bit
side outputs is present
HBF— HB1:4 Failure Bit
bridge outputs is present.
WINDOW WATCHDOG
to recover from, e.g. code runaways, or similar conditions.
the watchdog clear has not only to occur, but be done at a
certain time frame / window.
Normal mode
mode, and is halted in Stop and Sleep mode. On setting the
WDRE bit, the watchdog functionality is activated. Once this
function is enabled, it is not possible to disable it via software.
Reset clears the WDRE bit.
be cleared in the Window Open frame. This is done by writing
a logic “1” to the WDRST bit in the Watchdog Control register
(WDCTL). The actual reset of the watchdog counter occurs at
the end of the corresponding SPI transmission, with the rising
edge of the SS signal.
This read only bit is a copy of the HVDDOCF bit in the High
This read only bit is set if a fail condition on one of the high
This read only bit is set if a fail condition on one of the half-
The window watchdog is used to supervise the device, and
The use of a window watchdog adds additional safety, as
The window watchdog function is only available in Normal
To prevent a Watchdog reset, the Watchdog timer has to
1 = HVDD pin fail
0 = HVDD normal operating
1 = HS1:3 pin fail
0 = HS1:3 normal operating
1 = HB1:4 pin over-current fail
0 = HB1:4 normal operating
HS1OCF
HS2OCF
HS3OCF
HB1OCF
HB2OCF
HB3OCF
HB4OCF
Figure 27. HBF Flag Generation
Figure 26. HSF Flag Generation
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
HBF
HSF
908E621
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