MM908E622ACDR2 FREESCALE [Freescale Semiconductor, Inc], MM908E622ACDR2 Datasheet - Page 29

• Manufacturer Part Number: MM908E622ACDR2
• Description: Integrated Quad Half-Bridge, Triple High-Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

RESETS
source.
RESET SOURCE
High Temperature Reset
the chip temperature exceeds a certain temperature, a reset
(HTR) is generated. The reset is flagged by bit HTR in the
Interrupt Flag Register. A HTR event will reset all registers in
the SPI excluding the RSR.
Mask register.
destruction of the part in cases of high temperature. This
bit was foreseen for test purposes only!
Watchdog Reset
watchdog time-out or wrong watchdog timer reset. Reset is
flagged by bit WDR in the Reset Status Register. A Watchdog
reset event will reset all registers in the SPI excluding the
RSR.
Main VREG Low Voltage Reset
falls below a certain threshold, it will pull down the RST_A
terminal. Reset is flagged by bit LVR in the Reset Status
RST_A
Analog Integrated Circuit Device Data
Freescale Semiconductor
The 908E622 has four internal and one external reset
The device is protected against high temperature. When
The HTR can be disabled by bit HTRD in the Interrupt
Note: Disabling the high temperature reset can lead to
The WatchDog module generates a reset, because of a
The LVR is related to the Main VDD. In case the voltage
VDD
after reset event is
MONO FLOP
Pulse Duration
removed
Figure 15. Internal Reset Routing
Reset SPI Register
Clear RSR and set
(not RSR)
POR Bit
(1.25 ms typical), after the reset event is gone.
Register. A LVR event will reset all register in the SPI
excluding the RSR.
Power On Reset
device detects a power on the POR bit in the Reset Status
Register (RSR) is set. A power on reset will reset all register
in the SPI including the RSR and set the POR bit.
terminal low for t
value (above LVR Threshold). Also see
Reset terminal / external Reset
RST_A terminal. The reset event is flagged by bit PINR in the
reset status register.
Reset Status Register
the last reset. A power-on reset sets the POR bit and clears
all other bits in the Reset Status Register. All bits can be
cleared by writing a one to the corresponding bit. Uncleared
bits remain set as long as they are not cleared by a power-on
reset or by software.
Each internal reset event will cause a reset pin low for t
The POR is related to the internal 5V supply. In case the
The Power On Reset circuitry will force the RST_A
An external reset can be applied by pulling down the
This register contains five flags that shows the source of
SPI REGISTERS
RSR
RST
WDRE
HTRD
after the V
HTR Reset Sensor
WD Reset Sensor
DD
Functional Device Operation
has reached its nominal
Figure
POR internal VREG
LVR Main VREG
Operational Modes
10, page 20).
908E622
RST
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