MM908E622ACDR2 FREESCALE [Freescale Semiconductor, Inc], MM908E622ACDR2 Datasheet - Page 44

• Manufacturer Part Number: MM908E622ACDR2
• Description: Integrated Quad Half-Bridge, Triple High-Side and EC Glass Driver with Embedded MCU and LIN for High End Mirror
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

EC Status and Control Register (ECSCTL)
ECON — Electrochrome Circuitry enable Bit
electrochrome circuitry.
Reset clears the ECON bit.
ECOLT — Electrochrome Circuitry Open Load Test Bit
electrochrome circuitry. If this bit is set the EC Glass
functionality is ceased.
Reset clears the ECOLT bit.
ECRON — EC Resistor enable Bit
electrochrome circuitry.
Reset clears the ECRON bit.
by transistor T2 only. The enable of T1 will switch the VSUP
voltage via the external EC resistor to the EC glass.
ECOCF — EC Output Overcurrent Flag Bit
EC output (short to VSUP/ short to GND). Clear ECOCF and
enable the EC circuitry by writing a logic [1] to ECOCF.
Writing a logic [0] to ECOCF has no effect.
Reset clears the ECOCF bit.
ECOLF — EC Open Load Flag Bit
EC output.
Clear ECOLF and disable the EC circuitry by writing a logic
[1] to ECOLF. Writing a logic [0] to ECOLF has no effect.
Reset clears the ECOLF bit.
44
908E622
Functional Device Operation
Operational Modes
Reset
Read
Write
This read/write bit enables transistor T2 of the
This read/write bit enables the open load test for the
This read/write bit enables transistor T1 of the
Note: Controlling the output voltage on terminal EC is done
This read/write flag is set on short circuit condition at the
This read/write flag is set on an open load condition of the
1 = T2 EC circuitry enabled
0 = T2 EC circuitry disabled
1 = EC Open Load circuitry enabled
0 = EC Open Load circuitry disabled
1 = T1 EC circuitry enabled
0 = T1 EC circuitry disabled
1 = short circuit condition on EC output detected
0 = no short circuit condition on EC output detected
1 = open load condition on EC output detected
0 = no open load condition on EC output detected
ECON
Bit7
Register Name and Address: ECSCTL - $05
0
ECOLT
6
0
ECRON
5
0
4
0
0
3
0
0
2
0
0
ECOC
1
F
0
ECOLF
Bit0
0
System Control Register (SYSCTL)
PSON — Power Stages On Bit
high-sides, LIN transmitter, A0 Current Sources and HVDD
output).
Reset clears the PSON bit.
STOP — Change to STOP Mode Bit
Operational Modes on page
Reset or CPU interrupt requests clear the STOP bit.
to be “0”. Otherwise the STOP command will not be
executed.
SLEEP — Change to SLEEP Mode Bit
Operational Modes on page
Reset or CPU interrupt requests clear the SLEEP bit.
have to be “0”. Otherwise the SLEEP command will not be
executed.
HTIS0-1 — High Temperature Interrupt Shutdown Bits
High Temperature Interrupt (HTI).
Reset clears the HTIS0-1 bits.
and the high-side FET of the half-bridges HB1:4.
of the half-bridges HB1:4.
Reset
Read
Write
This read/write bit enables the power stages (half bridges,
This write bit instructs the chip to enter Stop mode
In order to safely Stop mode all other bits (Bit7-Bit2) have
This write bit instructs the chip to enter Sleep mode
In order to safely enter Sleep mode all other bits (Bit7-Bit2)
This read/write bits selects the power stage behavior at
The HTIS0 bit selects the behavior of the high-side HS1:3
The HTIS1 bit selects the behavior of the low-side drivers
1 = power stages enabled
0 = power stages disabled
1 = go to Stop mode
0 = not in stop mode
1 = go to Sleep mode
0 = not in sleep mode
1 = automatic HTI shutdown of the high-side drivers
0 = automatic HTI shutdown of the high-side drivers
1 = automatic HTI shutdown of the low-side drivers
PSON
Bit7
disabled
enabled
disabled
Register Name and Address: SYSCTL - $00
0
STOP
6
0
0
SLEEP
Analog Integrated Circuit Device Data
5
0
0
HTIS1
24).
24).
4
0
Freescale Semiconductor
HTIS0
3
0
VIS
2
0
SRS1
1
0
(See
(See
SRS0
Bit0
0