SL811ST CYPRESS [Cypress Semiconductor], SL811ST Datasheet - Page 22

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SL811ST

Manufacturer Part Number
SL811ST
Description
SL811S/T USB Dual Speed Slave Controller
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

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7.5
7.5.1
Note: nCS can be held low for multiple write cycles provided nWR is cycled.
Note:
Document #: 38-08009 Rev. **
10. I/O Write Cycle Time in Auto Inc Mode is 150 ns minimum.
twr
twcsu
twshld
twasu
twahld
twdsu
twdhld
tcscs
Parameter
Bus Interface Timing Requirements
I/O Write Cycle
nWR
A0
D0-D7
nCS
Write pulse width
Chip select set-up to nWR
Chip select hold time
A0 address set-up time
A0 address hold time
Data to write low set-up time
Data hold time after write high
nCS inactive to nCS
twcsu
twasu
twdsu
I/O Write Cycle to Register or Memory Buffer
Description
twr
[10]
Register or Memory
asserted
Address
twshld
85 ns
twahld
twdhld
65 ns
65 ns
10 ns
60 ns
Min.
0 ns
0 ns
5 ns
[10]
Tcscs See Note.
DATA
twdsu
Typical
twdhld
SL811S/T
Page 22 of 27
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