KSZ8895 INFINEON [Infineon Technologies AG], KSZ8895 Datasheet - Page 11

• Manufacturer Part Number: KSZ8895
• Description: Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII interface
• Manufacturer: INFINEON [Infineon Technologies AG]

Micrel, Inc.
KSZ8895MQ/RQ/FMQ
List of Figures
Figure 1. Typical Straight Cable Connection ............................................................................................................... 27
Figure 2. Typical Crossover Cable Connection ........................................................................................................... 28
Figure 3. Auto-Negotiation ........................................................................................................................................... 29
Figure 4. Destination Address Lookup Flow Chart, Stage 1 ........................................................................................ 34
Figure 5. Destination Address Resolution Flow Chart, Stage 2................................................................................... 35
Figure 6. 802.1p Priority Field Format.......................................................................................................................... 42
Figure 7. Tail Tag Frame Format .................................................................................................................................. 45
Figure 8. KSZ8895MQ/RQ/FMQ EEPROM Configuration Timing Diagram ................................................................ 49
Figure 9. SPI Write Data Cycle .................................................................................................................................... 50
Figure 10. SPI Read Data Cycle .................................................................................................................................. 50
Figure 11. SPI Multiple Write ....................................................................................................................................... 51
Figure 12. SPI Multiple Read ....................................................................................................................................... 51
Figure 13. EEPROM Interface Input Receive Timing Diagram.................................................................................. 102
Figure 14. EEPROM Interface Output Transmit Timing Diagram .............................................................................. 102
Figure 15. SNI Input Timing ....................................................................................................................................... 103
Figure 16. SNI Output Timing .................................................................................................................................... 103
Figure 17. MAC Mode MII Timing – Data Received from MII .................................................................................... 104
Figure 18. MAC Mode MII Timing – Data Transmitted from MII ................................................................................ 104
Figure 19. PHY Mode MII Timing – Data Received from MII..................................................................................... 105
Figure 20. PHY Mode MII Timing – Data Transmitted from MII................................................................................. 105
Figure 21. RMII Timing – Data Received from RMII .................................................................................................. 106
Figure 22. RMII Timing – Data Transmitted to RMII .................................................................................................. 106
Figure 23. SPI Input Timing ....................................................................................................................................... 107
Figure 24. SPI Output Timing..................................................................................................................................... 108
Figure 25: Auto-Negotiation Timing ........................................................................................................................... 109
Figure 26. MDC/MDIO Timing.................................................................................................................................... 110
Figure 27. Reset Timing ............................................................................................................................................. 111
Figure 28. Recommended Reset Circuit .................................................................................................................... 112
Figure 29. Recommended Circuit for Interfacing with CPU/FPGA Reset.................................................................. 112
11
January 2011
M9999-012011-1.2