PIC12F683-E/MD MICROCHIP [Microchip Technology], PIC12F683-E/MD Datasheet - Page 101

• Manufacturer Part Number: PIC12F683-E/MD
• Description: 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 12-10:
12.8
If
programmed, the on-chip program memory can be
read out using ICSP
12.9
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are
readable and writable during Program/Verify mode.
Only the Least Significant 7 bits of the ID locations are
used.
© 2007 Microchip Technology Inc.
Instruction Flow
Note
Note:
(INTCON<1>)
(INTCON<7>)
the
CLKOUT
Instruction
Instruction
Executed
INTF flag
Fetched
INT pin
GIE bit
1:
2:
3:
4:
OSC1
Code Protection
ID Locations
code
PC
The entire data EEPROM and Flash pro-
gram memory will be erased when the
code protection is turned off. See the
“PIC12F6XX/16F6XX Memory
Programming Specification” (DS41204)
for more information.
(4)
XT, HS or LP Oscillator mode assumed.
T
GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.
CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
OST
Inst(PC) = Sleep
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
protection
Inst(PC – 1)
= 1024 T
™
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
for verification purposes.
OSC
(drawing not to scale). This delay does not apply to EC and RCIO Oscillator modes.
bit(s)
Inst(PC + 1)
PC + 1
Sleep
have
Processor in
not
Sleep
PC + 2
been
T
OST (2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
PC + 2
Dummy Cycle
(3)
PC + 2
Dummy Cycle
PIC12F683
Inst(0004h)
0004h
DS41211D-page 99
Inst(0005h)
Inst(0004h)
0005h