PIC12F683-E/P Microchip Technology Inc., PIC12F683-E/P Datasheet
PIC12F683-E/P
Specifications of PIC12F683-E/P
Related parts for PIC12F683-E/P
PIC12F683-E/P Summary of contents
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... Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and foreign patents and applications may be issued or pending. 2004 Microchip Technology Inc. PIC12F683 Data Sheet 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology Preliminary DS41211B ...
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... The Company’s quality system processes and procedures are for its PICmicro ® 8-bit MCUs EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary 2004 Microchip Technology Inc. ® code hopping devices, Serial OQ ...
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... Flash/Data EEPROM Retention: > 40 years Program Memory Device Flash (words) SRAM (bytes) PIC12F683 2048 2004 Microchip Technology Inc. PIC12F683 nanoWatt Technology Low-Power Features • Standby Current 2.0V, typical • Operating Current kHz, 2.0V, typical - 100 MHz, 2.0V, typical • Watchdog Timer Current ...
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... PIC12F683 Pin Diagram 8-pin PDIP, SOIC, DFN-S GP5/T1CKI/OSC1/CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP3/MCLR/V DS41211B-page GP0/AN0/CIN+/ICSPDAT/ULPWU 3 6 GP1/AN1/CIN-/ GP2/AN2/T0CKI/INT/COUT/CCP1 PP Preliminary /ICSPCLK REF 2004 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2004 Microchip Technology Inc. Preliminary PIC12F683 DS41211B-page 3 ...
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... PIC12F683 NOTES: DS41211B-page 4 Preliminary 2004 Microchip Technology Inc. ...
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... The PIC12F683 is covered by this data sheet available in 8-pin PDIP, SOIC and DFN-S packages. Figure 1-1 shows a block diagram of the PIC12F683 device. Table 1-1 shows the pinout description. ...
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... PIC12F683 TABLE 1-1: PIC12F683 PINOUT DESCRIPTION Name Function GP5/T1CKI/OSC1/CLKIN GP5 T1CKI OSC1 CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP4 AN3 T1G OSC2 CLKOUT GP3/MCLR/V GP3 PP MCLR V PP GP2/AN2/T0CKI/INT/COUT/CCP1 GP2 AN2 T0CKI INT COUT CCP1 GP1/AN1/CIN-/V /ICSPCLK GP1 REF AN1 CIN- V REF ICSPCLK GP0/AN0/CIN+/ICSPDAT/ULPWU GP0 ...
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... Program Memory Organization The PIC12F683 has a 13-bit program counter capable of addressing program memory space. Only the first (0000h-07FFh) for the PIC12F683 is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1) ...
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... The Special Function Registers associated with the “core” are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. DS41211B-page 8 FIGURE 2-2: DATA MEMORY MAP OF THE PIC12F683 File Address (1) Indirect addr. 00h TMR0 01h ...
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... TABLE 2-1: PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 83 01h TMR0 Timer0 Module’s Register 02h PCL Program Counter’s (PC) Least Significant Byte ...
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... PIC12F683 TABLE 2-2: PIC12F683 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 83 81h OPTION_REG GPPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte ...
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... Status bits. For other instructions not affecting any Status bits, see the “Instruction Set Summary”. Note 1: Bits IRP and RP1 (Status<7:6>) are not used by the PIC12F683 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products ...
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... Note 1: A dedicated 16-bit WDT postscaler is available for the PIC12F683. See Section 12.6 “Watchdog Timer (WDT)” for more information. Legend Readable bit - n = Value at POR DS41211B-page 12 Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT by setting PSA bit to ‘ ...
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... R/W-0 R/W-0 R/W-0 R/W-0 T0IE INTE GPIE T0IF (1) ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC12F683 R/W-0 R/W-0 INTF GPIF bit Bit is unknown DS41211B-page 13 ...
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... PIC12F683 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) R/W-0 R/W-0 EEIE ADIE bit 7 bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 = Enables the EE write complete interrupt ...
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... R/W-0 U-0 R/W-0 R/W-0 CCP1IF — CMIF OSFIF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC12F683 R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown DS41211B-page 15 ...
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... PIC12F683 2.2.2.6 PCON Register The Power Control (PCON) register contains flag bits (see Table 12-2) to differentiate between a: • Power-on Reset (POR) • Brown-out Detect (BOD) • Watchdog Timer Reset (WDT) • External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOD ...
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... Application Note AN556, “Implementing a Table Read” (DS00556). 2.3.2 STACK The PIC12F683 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...
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... PIC12F683 FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F683 Direct Addressing (1) From Opcode RP1 RP0 6 Bank Select Location Select 00h Data Memory 7Fh Bank 0 For memory map detail, see Figure 2-2. Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. ...
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... Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz 2004 Microchip Technology Inc. The PIC12F683 can be configured in one of eight clock modes – External clock with I/O on GP4 – Low gain crystal or Ceramic Resonator Oscillator mode – Medium gain crystal or Ceramic Resonator Oscillator mode ...
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... External Clock Modes 3.3.1 OSCILLATOR START-UP TIMER (OST) If the PIC12F683 is configured for LP modes, the Oscillator Start-up Timer (OST) counts 1024 oscil- lations from the OSC1 pin, following a Power-on Reset (POR) and the Power-up Timer (PWRT) has expired (if configured wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended ...
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... I/O pin. The I/O pin becomes bit 4 of GPIO (GP4). Figure 3-6 shows the RCIO mode connections. Preliminary PIC12F683 CERAMIC RESONATOR OPERATION ( MODE) PIC12F683 OSC1 To Internal Logic (3) Sleep F ( OSC2 ( may be required for S varies with the oscillator MODE Internal OSC1 Clock PIC12F683 OSC2/CLKOUT / 100 k EXT C > EXT DS41211B-page 21 ...
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... Internal Clock Modes The PIC12F683 has two independent, internal oscilla- tors that can be configured or selected as the system clock source. 1. The HFINTOSC (High-Frequency Internal Oscil- lator) is factory calibrated and operates at 8 MHz. ...
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... Monitor (FSCM) and peripherals, are not affected by the change in frequency. U-0 U-0 R/W-0 R/W-0 — — TUN4 TUN3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC12F683 R/W-0 R/W-0 R/W-0 TUN2 TUN1 TUN0 bit Bit is unknown DS41211B-page 23 ...
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... PIC12F683 3.4.3 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC uncalibrated (approximate) 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). 31 kHz can be selected via software using the IRCF bits (see Section 3.4.4 “Frequency Select Bits (IRCF)”). The ...
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... Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit (OSCCON<3>) to remain clear. When the PIC12F683 is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.3.1 “Oscillator Start-up (OST)” ...
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... PIC12F683 3.6.3 CHECKING EXTERNAL/INTERNAL CLOCK STATUS Checking the state of the OSTS bit (OSCCON<3>) will confirm if the PIC12F683 is running from the external clock source as defined by the FOSC bits in the Configuration Word register (CONFIG) or the internal oscillator. FIGURE 3-7: TWO-SPEED START- INTOSC T T OST ...
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... The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction modification of the SCS bit. While in Fail-Safe condition, the PIC12F683 uses the internal oscillator as the system clock source. The IRCF bits (OSCCON<6:4>) can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition. ...
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... PIC12F683 3.7.2 RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited a Reset or Sleep con- dition and the Oscillator Start-up Timer (OST) has expired. If the external clock mode, monitoring will begin immediately following these events ...
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... TMR2IE TMR1IE 000- 0000 0000 0000 (2) IRCF1 IRCF0 OSTS HTS LTS — TUN4 TUN3 TUN2 TUN1 MCLRE PWRTE WDTE FOSC2 FOSC1 Preliminary PIC12F683 Bit 0 Value on: Value on POR, BOD all other Resets SCS -110 x000 -110 x000 TUN0 ---0 0000 ---u uuuu FOSC0 — — DS41211B-page 29 ...
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... PIC12F683 NOTES: DS41211B-page 30 Preliminary 2004 Microchip Technology Inc. ...
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... MOVLW 0Ch MOVWF TRISIO BCF STATUS,RP0 4.2 Additional Pin Functions Every GPIO pin on the PIC12F683 has an interrupt-on- change option and a weak pull-up option. GP0 has an Ultra Low-Power Wake-up option. The next three sections describe these functions. 4.2.1 WEAK PULL-UPS Each of the GPIO pins, except GP3, has an individually configurable weak internal pull-up ...
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... PIC12F683 REGISTER 4-2: TRISIO – GPIO TRI-STATE REGISTER (ADDRESS: 85h) U-0 — bit 7 bit 7-6: Unimplemented: Read as ‘0’ bit 5-0: TRISIO<5:0>: GPIO Tri-State Control bit 1 = GPIO pin configured as an input (tri-stated GPIO pin configured as an output Note 1: TRISIO<3> always reads ‘1’. ...
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... The Ultra Low-Power Wake-up peripheral can also be configured as a simple Programmable Low-Voltage Detect or temperature sensor. Note: For more information, refer to the Applica- tion Note AN879, “Using the Microchip Ultra (DS00879). Preliminary PIC12F683 R/W-0 R/W-0 R/W-0 IOC2 IOC1 IOC0 bit Bit is unknown ...
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... PIC12F683 EXAMPLE 4-2: ULTRA LOW-POWER WAKE-UP INITIALIZATION BCF STATUS,RP0 ;Bank 0 BSF GPIO,0 ;Set GP0 data latch MOVLW H’7’ ;Turn off MOVWF CMCON0 ; comparator BSF STATUS,RP0 ;Bank 1 BCF ANSEL,0 ;GP0 to digital I/O BCF TRISIO,0 ;Output high to CALL CapDelay ; charge capacitor BSF PCON,ULPWUE ...
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... GPIO TRISIO RD TRISIO RD GPIO IOC RD IOC Interrupt-on- change To TMR0 To INT To A/D Converter Note 1: Comparator mode and ANSEL determines Analog Input mode. Preliminary PIC12F683 BLOCK DIAGRAM OF GP2 Analog Input Mode Weak GPPU Analog COUT Input Enable Mode COUT 1 0 I/O pin Analog ...
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... PIC12F683 4.2.4.4 GP3/MCLR/V PP Figure 4-4 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset with weak pull-up FIGURE 4-4: BLOCK DIAGRAM OF GP3 MCLRE Data Bus MCLRE Reset TRISIO ...
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... CK Q TRISIO INTOSC RD Mode TRISIO RD GPIO IOC EN RD IOC Q EN Interrupt-on- change RD GPIO To TMR1 or CLKGEN Note 1: Timer1 LP oscillator enabled. 2: When using Timer1 with LP oscillator, the Schmitt Trigger is bypassed. 2004 Microchip Technology Inc. ( Weak V DD I/O pin Preliminary PIC12F683 DS41211B-page 37 ...
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... PIC12F683 TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO Addr Name Bit 7 Bit 6 05h GPIO — — 0Bh/8Bh INTCON GIE PEIE 19h CMCON0 — COUT 81h OPTION_REG GPPU INTEDG 85h TRISIO — — 95h WPU — — 96h IOC — — 9Fh ANSEL — ...
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... Interrupt Service Routine before re-enabling this interrupt. The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut off during Sleep. 8-bit Prescaler PSA 8 PS<2:0> 16-bit 16 PSA WDTPS<3:0> Preliminary PIC12F683 edge (T0SE) control ® Mid-Range MCU Family Data Bus 8 1 SYNC 2 TMR0 Cycles ...
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... PIC12F683 5.3 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore ...
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... TIMER1 MODULE WITH GATE CONTROL The PIC12F683 has a 16-bit timer. Figure 6-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: • 16-bit timer/counter (TMR1H:TMR1L) • Readable and writable • Internal or external clock selection • Synchronous or asynchronous operation • ...
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... PIC12F683 6.1 Timer1 Modes of Operation Timer1 can operate in one of three modes: • 16-bit timer with prescaler • 16-bit synchronous counter • 16-bit asynchronous counter In Timer mode, Timer1 is incremented on every instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI ...
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... R = Readable bit - n = Value at POR 2004 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (1) (2) /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC12F683 R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown DS41211B-page 43 ...
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... PIC12F683 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can gen- erate an interrupt on overflow, which will wake-up the processor ...
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... TMR2 is not cleared when T2CON is written. R/W-0 R/W-0 R/W-0 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC12F683 /4) has a prescale option OSC R/W-0 R/W-0 R/W-0 bit Bit is unknown DS41211B-page 45 ...
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... PIC12F683 7.2 Timer2 Interrupt The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 7-1: ...
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... Figure 8-3. R-0 U-0 R/W-0 R/W-0 — CINV CIS W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC12F683 R/W-0 R/W-0 R/W-0 CM2 CM1 CM0 bit Bit is unknown DS41211B-page 47 ...
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... PIC12F683 8.1 Comparator Operation A single comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output. When the analog input at V than the analog input V -, the output of the comparator digital low level. When the analog input at V ...
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... A COUT GP0/CIN+ A GP2/COUT D Multiplexed Input with Internal Reference CM<2:0> = 110 GP1/CIN- A COUT GP0/CIN+ A GP2/COUT D CIS = Comparator Input Switch (CMCON0<3>) Preliminary PIC12F683 Off (Read as ‘0’) COUT From CV Module REF CIS = 0 CIS = 1 COUT From CV Module REF CIS = 0 CIS = 1 COUT From CV Module REF ...
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... PIC12F683 FIGURE 8-4: COMPARATOR OUTPUT BLOCK DIAGRAM CMSYNC To TMR1 To COUT pin To Data Bus RD CMCON Set CMIF bit Note 1: Comparator output is latched on falling edge of T1 clock source. REGISTER 8-2: CMCON1 – COMPARATOR CONTROL REGISTER 1 (ADDRESS: 1Ah) U-0 — bit 7 bit 7-2: Unimplemented: Read as ‘0’ ...
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... Timer1 increments on the rising edge of its clock source. See Figure 8-4, Comparator Output Block Diagram and Figure 6-1, Timer1 on the PIC12F683 Block Diagram for more information recommended to synchronize the comparator with Timer1 by setting the CMSYNC bit when the compara- tor is used as the Timer1 gate source ...
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... PIC12F683 8.6 Comparator Reference The comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. The VRCON register, Register 8-3, controls the voltage reference module shown in Figure 8-5. 8.6.1 CONFIGURING THE VOLTAGE REFERENCE The voltage reference can output 32 distinct voltage levels high range and low range ...
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... Enable bit drain and CV DD Value Selection 0 VR <3:0> (VR<3:0>/24 REF (VR<3:0>/32 REF Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC12F683 R/W-0 R/W-0 R/W-0 VR2 VR1 VR0 bit REF Bit is unknown DS41211B-page 53 ...
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... PIC12F683 TABLE 8-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Address Name Bit 7 Bit 6 0Bh/8Bh INTCON GIE PEIE 0Ch PIR1 EEIF ADIF CCP1IF 19h CMCON0 — COUT 1Ah CMCON1 — — 85h TRISIO — — TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 8Ch PIE1 ...
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... The voltage reference (A/D) allows used in the conversion is software selectable to either voltage applied by the V DD shows the block diagram of the A/D on the PIC12F683 VCFG = 0 V VCFG = 1 REF A/D GO/DONE ...
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... PIC12F683 TABLE 9-1: T vs. DEVICE OPERATING FREQUENCIES AD A/D Clock Source ( Operation ADCS<2:0> OSC 000 4 T 100 OSC 8 T 001 OSC 16 T 101 OSC 32 T 010 OSC 64 T 110 OSC A/D RC x11 Legend: Shaded cells are outside of recommended range. Note 1: The A/D RC source has a typical T ...
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... ADRESH and ADRESL registers are Loaded, GO bit is Cleared, ADIF bit is Set, Holding Capacitor is Connected to Analog Input ADRESH bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 Preliminary PIC12F683 sample. Instead, the ADRESL LSB bit 0 Unimplemented: Read as ‘0’ LSB bit 0 10-bit A/D Result ...
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... PIC12F683 REGISTER 9-1: ADCON0 – A/D CONTROL REGISTER (ADDRESS: 1Fh) R/W-0 R/W-0 ADFM VCFG bit 7 bit 7 ADFM: A/D Result Formed Select bit 1 = Right justified 0 = Left justified bit 6 VCFG: Voltage Reference bit pin REF bit 5-4 Unimplemented: Read as ‘0’ bit 3-2 CHS< ...
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... Value at POR 2004 Microchip Technology Inc. R/W-0 R/W-0 R/W-1 ADCS1 ADCS0 ANS3 ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC12F683 R/W-1 R/W-1 R/W-1 ANS2 ANS1 ANS0 bit Bit is unknown DS41211B-page 59 ...
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... PIC12F683 9.1.7 CONFIGURING THE A/D After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRISIO bits selected as inputs. To determine sample time, see Section 15.0 “Electri- cal Specifications” ...
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... R ) In(1/2047 has no effect on the equation, since it cancels itself out not discharged after each conversion. HOLD V DD Sampling Switch LEAKAGE V = 0.6V T ± 500 Preliminary PIC12F683 , see ACQ ® Mid-Range MCU Family Reference SS C HOLD = DAC capacitance = 120 Sampling Switch (k ) DS41211B-page 61 ...
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... This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise from the conversion. When the conversion is complete, the GO/DONE bit is cleared and the result is loaded into the ADRESH:ADRESL registers. FIGURE 9-5: PIC12F683 A/D TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh ...
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... CHS1 CHS0 GO/DONE TRISIO1 — CMIE OSFIE TMR2IE ADCS0 ANS3 ANS2 ANS1 Preliminary PIC12F683 Value on Value on: Bit 0 all other POR, BOD Resets GP0 --xx xxxx --uu uuuu GPIF 0000 0000 0000 0000 TMR1IF 000- 0000 000- 0000 xxxx xxxx uuuu uuuu ADON ...
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... PIC12F683 NOTES: DS41211B-page 64 Preliminary 2004 Microchip Technology Inc. ...
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... EEDAT • EEADR EEDAT holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. PIC12F683 has 256 bytes of data EEPROM with an address range from 0h to FFh. REGISTER 10-1: EEDAT – EEPROM DATA REGISTER (ADDRESS: 9Ah) ...
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... PIC12F683 10.1 EECON1 and EECON2 Registers EECON1 is the control register with four low-order bits physically implemented. The upper four bits are non- implemented and read as ‘0’. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software ...
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... If proper refreshes occurred, then the lone memory location would have to be refreshed six times for the data to remain correct. Preliminary PIC12F683 ;Bank 1 ;EEDAT not changed ;from previous write ;YES, Read the ...
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... PIC12F683 10.5 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) EEPROM write. ...
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... R/W-0 R/W-0 R/W-0 — DC1B1 DC1B0 CCP1M3 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC12F683 CCP MODE – TIMER RESOURCES REQUIRED Timer Resource Timer1 Timer1 Timer2 R/W-0 R/W-0 R/W-0 CCP1M2 CCP1M1 CCP1M0 ...
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... PIC12F683 11.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin GP2/AN2/T0CKI/INT/COUT/CCP1. An event is defined as one of the following and is configured by CCP1CON<3:0>: • Every falling edge • Every rising edge • Every 4th rising edge • Every 16th rising edge When a capture is made, the interrupt request flag bit, CCP1IF (PIR1< ...
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... TMR2IF — — — — T1GSS CMSYNC ---- --10 ---- --10 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000 — CMIE OSFIE TMR2IE Preliminary PIC12F683 the GP2/AN2/T0CKI/INT/COUT/ Value on Value on Bit 1 Bit 0 all other POR, BOD Resets INTF GPIF 0000 0000 0000 0000 TMR1IF 000- 0000 000- 0000 ...
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... PIC12F683 11.3 PWM Mode (PWM) In Pulse Width Modulation mode, the CCP1 pin produces 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the GPIO data latch, the TRISIO<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level ...
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... For sensitive applications, disable the PWM module prior to modifying the duty cycle. 1.22 kHz 4.88 kHz 19.53 kHz 0xFFh 0xFFh 0xFFh Preliminary PIC12F683 F OSC log F • TMR2 Prescale Value PWM bits log(2) 78.12 kHz 156.3 kHz 208.3 kHz ...
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... PIC12F683 TABLE 11-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Addr Name Bit 7 Bit 6 Bit 5 0Bh/ INTCON GIE PEIE T0IE 8Bh 0Ch PIR1 EEIF ADIF CCP1IF 11h TMR2 Timer2 Module Register 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 ...
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... SPECIAL FEATURES OF THE CPU The PIC12F683 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: • Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Detect (BOD) • ...
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... PIC12F683 12.1 Configuration Bits The configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 12-1. These bits are mapped in program memory location 2007h. REGISTER 12-1: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h) — ...
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... See “PIC12F6XX/16F6XX Memory (DS41204) for more information. FCAL2 FCAL1 FCAL0 — POR1 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC12F683 memory space (2000h- Programming Specification” POR0 BOD2 BOD1 BOD0 bit Bit is unknown ...
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... PIC12F683 12.3 Reset The PIC12F683 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during Sleep d) MCLR Reset during normal operation e) MCLR Reset during Sleep f) Brown-out Detect (BOD) Some registers are not affected in any Reset condition; ...
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... For additional information, refer to the Application Note AN607, “Power-up Trouble Shooting” (DS00607). 12.3.2 MCLR PIC12F683 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. ...
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... Power-up Timer will be re-initialized. Once V rises above V BOD 64 ms Reset. 12.3.4.1 BOD Calibration The PIC12F683 stores the BOD calibration values in fuses located in the Calibration Word register (2008h). The Calibration Word register is not erased when using the specified bulk erase sequence in the “PIC12F6XX/ register 16F6XX Memory (DS41204) and thus, does not require reprogramming ...
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... Then, bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC12F683 device operating in parallel. Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers ...
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... PIC12F683 FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR ...
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... Preliminary PIC12F683 Wake-up from Sleep through Interrupt WDT Time-out uuuu uuuu uuuu uuuu uuuu uuuu ( (4) uuuq quuu uuuu uuuu --uu uuuu ---u uuuu ...
Page 86
... PIC12F683 TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Register Address Power-on Reset EECON1 9Ch ---- x000 EECON2 9Dh ---- ---- ADRESL 9Eh xxxx xxxx ANSEL 9Fh 1111 1111 Legend unchanged unknown, — = unimplemented bit, reads as ‘0’ value depends on condition. Note goes too low, Power-on Reset will be activated and registers will be affected differently. ...
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... Interrupts The PIC12F683 has 11 sources of interrupt: • External Interrupt GP2/INT • TMR0 Overflow Interrupt • GPIO Change Interrupts • 2 Comparator Interrupts • A/D Interrupt • Timer1 Overflow Interrupt • Timer2 Match Interrupt • EEPROM Data Write Interrupt • Fail-Safe Clock Monitor Interrupt • ...
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... PIC12F683 12.4.2 TMR0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing (INTCON<5>) bit. See Section 5.0 “Timer0 Module” for operation of the Timer0 module. FIGURE 12-7: INTERRUPT LOGIC IOC-GP0 IOC0 IOC-GP1 ...
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... Bit 2 T0IE INTE GPIE T0IF INTF CCP1IF — CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000 CCP1IE — CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000 Preliminary PIC12F683 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) Dummy Cycle = instruction cycle time. CY ...
Page 90
... W and Status registers). This must be implemented in software. Since the lower 16 bytes of all banks are common in the PIC12F683 (see Figure 2-2), temporary holding regis- ters, W_TEMP and STATUS_TEMP, should be placed in here. These 16 locations do not require banking and therefore, makes it easier to context save and restore. ...
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... Watchdog Timer (WDT) For PIC12F683, the WDT has been modified from previous PIC12F683 devices. The new WDT is code and functionally compatible with previous PIC12F683 WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to have a scaler value for the WDT and TMR0 at the same time ...
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... PIC12F683 REGISTER 12-3: WDTCON – WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 18h) U-0 — bit 7 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) ...
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... SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. Preliminary PIC12F683 DS41211B-page 91 ...
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... Program/Verify mode. Only the Least Significant 7 bits of the ID locations are used. 12.10 In-Circuit Serial Programming The PIC12F683 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for: • ...
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... PIC12F683 device. The debugging adapter is the only source of the ICD device. 2004 Microchip Technology Inc. When the ICD pin on the PIC12F683 ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2 ...
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... PIC12F683 NOTES: DS41211B-page 94 Preliminary 2004 Microchip Technology Inc. ...
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... INSTRUCTION SET SUMMARY The PIC12F683 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction ...
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... PIC12F683 TABLE 13-2: PIC12F683 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS f, d Add W and f ADDWF f, d AND W with f ANDWF f Clear f CLRF - Clear W CLRW f, d Complement f COMF f, d Decrement f DECF f, d Decrement f, Skip if 0 DECFSZ f, d Increment f INCF f, d Increment f, Skip if 0 ...
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... Operation: Status Affected: Description: BTFSC Syntax: k Operands: Operation: Status Affected: None Description: BTFSS f,d Syntax: Operands: Operation: Status Affected: Description: Preliminary PIC12F683 Bit Clear f [ label ] BCF f 127 (f<b>) None Bit ‘b’ in register ‘f’ is cleared. Bit Set f [ label ] BSF f,b 0 ...
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... PIC12F683 CALL Call Subroutine Syntax: [ label ] CALL k Operands 2047 Operation: (PC TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> Status Affected: None Description: Call subroutine. First, return address ( pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. ...
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... If ‘d’ the destination is file register ‘f’ itself. ‘d’ useful to test a file register since status flag Z is affected. Words: 1 Cycles: 1 Example: MOVF After Instruction Preliminary PIC12F683 INCFSZ f,d 127 (destination), MOVF f,d 127 1000 dfff ffff FSR value in FSR register ...
Page 102
... PIC12F683 MOVLW Move Literal to W Syntax: [ label ] MOVLW k Operands 255 Operation: k (W) Status Affected: None Encoding: 11 00xx Description: The eight-bit literal ‘k’ is loaded into the W register. The don’t cares will assemble as ‘0’s . Words: 1 Cycles: 1 Example: MOVLW 0x5A After Instruction ...
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... Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: Example: RRF Syntax: Operands: Operation: Status Affected: Description: Preliminary PIC12F683 Rotate Left f through Carry [ label ] RLF f 127 d [0,1] See description below C 00 1101 dfff ffff The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘ ...
Page 104
... PIC12F683 SLEEP Syntax: [ label ] SLEEP Operands: None Operation: 00h WDT, 0 WDT prescaler Status Affected: TO, PD Description: The Power-down status bit, PD, is cleared. Time-out status bit, TO, is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. ...
Page 105
... The MPASM assembler features include: • Integration into MPLAB IDE projects • User defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process Preliminary PIC12F683 ® ® standard HEX DS41211B-page 103 ...
Page 106
... PIC12F683 14.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. ...
Page 107
... MPLAB PM3 connects to the host PC via an RS-232 or USB cable. MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorpo- rates an SD/MMC card for file storage and secure data applications. Preliminary PIC12F683 development tool, TM (ICSP TM ) ...
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... PIC12F683 14.14 PICSTART Plus Development Programmer The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It con- nects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices pins ...
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... PICDEM MSC demo boards for Switching mode power supply, high-power IR driver, delta sigma ADC and flow rate sensor Check the Microchip web page and the latest Product Selector Guide for the complete list of demonstration and evaluation kits. ® IDE software, Preliminary PIC12F683 TM development DS41211B-page 107 ...
Page 110
... PIC12F683 NOTES: DS41211B-page 108 Preliminary 2004 Microchip Technology Inc. ...
Page 111
... Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin, rather than pulling this pin directly to V 2004 Microchip Technology Inc. ........................................................................... -0. ∑ DIS the MCLR pin, inducing currents greater than 80 mA, may cause latch-up Preliminary PIC12F683 + 0.3V ∑ {( ∑( DS41211B-page 109 ...
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... PIC12F683 FIGURE 15-1: PIC12F683 VOLTAGE-FREQUENCY GRAPH, -40°C 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS41211B-page 110 Frequency (MHz) Preliminary +125° 2004 Microchip Technology Inc. ...
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... DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Supply Voltage DD D001 D001C D001D D002 V RAM Data Retention DR (1) Voltage D003 V V Start Voltage to POR DD ensure internal Power-on Reset signal D004 S V Rise Rate to ensure VDD DD internal Power-on Reset ...
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... PIC12F683 15.2 DC Characteristics: PIC12F683-I (Industrial) DC CHARACTERISTICS Param Device Sym No. Characteristics (1,2) D010 I Supply Current DD D011 D012 D013 D014 D015 D016 D017 D018 Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
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... DC Characteristics: PIC12F683-I (Industrial) (Continued) DC CHARACTERISTICS Param Device Sym No. Characteristics D020 I Power-down Base PD (4) Current D021 D022 D023 D024 D025 D026 Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
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... PIC12F683 15.3 DC Characteristics: PIC12F683-E (Extended) DC CHARACTERISTICS Param Device Sym No. Characteristics (1,2) D010E I Supply Current DD D011E D012E D013E D014E D015E D016E D017E D018E Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
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... DC Characteristics: PIC12F683-E (Extended) (Continued) DC CHARACTERISTICS Param Device Sym No. Characteristics D020E I Power-down Base PD (4) Current D021E D022E D023E D024E D025E D026E Legend: TBD = To Be Determined † Data in ‘Typ’ column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested ...
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... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 4: See Section 10.4.1 “Using the Data EEPROM” for additional information. DS41211B-page 116 PIC12F683-I (Industrial) PIC12F683-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C -40°C Min Typ† ...
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... DC Characteristics: PIC12F683-I (Industrial) PIC12F683-E (Extended) (Continued) DC CHARACTERISTICS Param Sym Characteristic No. D100 I Ultra Low-Power Wake-up ULP Current Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin D101 C All I/O pins IO Data EEPROM Memory D120 E Byte Endurance D D120A E Byte Endurance D D121 V V for Read/Write ...
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... PIC12F683 15.5 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings Fall ...
Page 121
... AC Characteristics: PIC12F683 (Industrial, Extended) FIGURE 15-3: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No. F External CLKIN Frequency OSC Oscillator Frequency 1 T External CLKIN Period ...
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... PIC12F683 TABLE 15-2: PRECISION INTERNAL OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No. F10 F Internal Calibrated OSC INTOSC Frequency F14 T Oscillator Wake-up from IOSCST Sleep Start-up Time* Legend: TBD = To Be Determined * These parameters are characterized but not tested. ...
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... 20, 21 +125°C A Min — — — — — 200 ns OSC 0 — — 100 0 — — Preliminary PIC12F683 New Value Typ† Max Units Conditions 75 200 ns (Note 1) 75 200 ns (Note 1) 35 100 ns (Note 1) 35 100 ns (Note 1) — (Note 1) — — ns (Note 1) — ...
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... PIC12F683 FIGURE 15-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset I/O pins FIGURE 15-6: BROWN-OUT DETECT TIMING AND CHARACTERISTICS VDD (Device in Brown-out Detect) Reset (due to BOD) Note delay only if PWRTE bit in Configuration Word register is programmed to ‘ ...
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... Typ† 2 — — 1024T OSC 28* 64 TBD TBD — — 2.025 — 100* — — — Preliminary PIC12F683 Max Units Conditions — 5V, -40°C to +85° Extended temperature 5V, -40°C to +85° Extended temperature — — OSC1 period OSC 132 5V, -40° ...
Page 126
... PIC12F683 FIGURE 15-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI T1CKI TMR0 or TMR1 TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No. 40* Tt0H T0CKI High Pulse Width 41* Tt0L T0CKI Low Pulse ...
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... Microchip Technology Inc +125°C Min Typ† Max Units No Prescaler 0 With Prescaler 20 No Prescaler 0 With Prescaler — — Preliminary PIC12F683 51 Conditions — — ns — — ns — — ns — — ns — — prescale value ( 16 DS41211B-page 125 ...
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... PIC12F683 TABLE 15-7: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Sym Characteristics V Input Offset Voltage OS V Input Common Mode Voltage CM C Common Mode Rejection Ratio MRR (1) T Response Time Comparator Mode Change Output Valid * These parameters are characterized but not tested. ...
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... TABLE 15-9: PIC12F683 A/D CONVERTER CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No. A01 N Resolution R A02 E Total Absolute ABS (1) Error* A03 E Integral Error IL A04 E Differential Error DL A05 E Full-scale Range FS A06 E Offset Error OFF A07 E Gain Error ...
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... A/D CLK A/D Data ADRES ADIF GO 132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 15-10: PIC12F683 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No. ...
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... A/D Data ADRES ADIF GO 132 Sample Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 15-11: PIC12F683 A/D CONVERSION REQUIREMENTS (SLEEP MODE) Standard Operating Conditions (unless otherwise stated) Operating temperature -40° Param Sym Characteristic No. ...
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... PIC12F683 NOTES: DS41211B-page 130 Preliminary 2004 Microchip Technology Inc. ...
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... DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and Tables are not available at this time. 2004 Microchip Technology Inc. PIC12F683 DS41211B-page 131 ...
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... PIC12F683 NOTES: DS41211B-page 132 2004 Microchip Technology Inc. ...
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... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2004 Microchip Technology Inc. Example 12F683-I /P017 0415 Example 12F683-E /SN0415 017 Example 12F683 -E/MF 0415 017 Preliminary PIC12F683 DS41211B-page 133 ...
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... PIC12F683 17.2 Package Details The following sections give the technical details of the packages. 8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width ...
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... L .019 .025 .030 .008 .009 .010 B .013 .017 .020 Preliminary PIC12F683 A2 MILLIMETERS MIN NOM MAX 8 1.27 1.35 1.55 1.75 1.32 1.42 1.55 0.10 0.18 0.25 5.79 6.02 6.20 3.71 3.91 3.99 4.80 4.90 5.00 0.25 0.38 ...
Page 138
... PIC12F683 8-Lead Plastic Dual Flat No Lead Package (MF) 6x5 mm Body (DFN-S) – Punch Singulated TOP VIEW α A1 Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Base Thickness Overall Length Molded Package Length Exposed Pad Length Overall Width Molded Package Width ...
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... Microchip Technology Inc. APPENDIX B: MIGRATING FROM OTHER PICmicro DEVICES This discusses some of the issues in migrating from other PICmicro devices to the PIC12F6XX family of devices. B.1 PIC12F675 to PIC12F683 TABLE B-1: FEATURE COMPARISON Feature Max Operating Speed Max Program Mem- ory (Words) SRAM (Bytes) A/D Resolution ...
Page 140
... PIC12F683 NOTES: DS41211B-page 138 Preliminary 2004 Microchip Technology Inc. ...
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... GP1 Pin....................................................................... 35 GP2 Pin....................................................................... 35 GP3 Pin....................................................................... 36 GP4 Pin....................................................................... 36 GP5 Pin....................................................................... 37 In-Circuit Serial Programming Connection.................. 93 Interrupt Logic ............................................................. 86 On-Chip Reset Circuit ................................................. 78 PIC12F683.................................................................... 5 PIC12F683 Clock Source ........................................... 19 Recommended MCLR Circuit ..................................... 79 Simplified PWM Mode................................................. 72 Timer1......................................................................... 41 Timer2......................................................................... 46 TMR0/WDT Prescaler................................................. 39 Watchdog Timer (WDT) .............................................. 89 Brown-out Detect (BOD) ..................................................... 80 Associated Registers .................................................. 81 Calibration ...
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... Compare Module. See Capture/Compare/PWM (CCP) Configuration Bits................................................................ 76 CPU Features ..................................................................... 75 D Data EEPROM Memory Associated Registers .................................................. 68 Code Protection .................................................... 65, 68 Data Memory Organization ................................................... 7 Map of the PIC12F683 .................................................. 8 DC and AC Characteristics Graphs and Tables........................... 131 DC Characteristics Extended ................................................................... 114 Industrial ................................................................... 112 Industrial and Extended .................................... 111, 116 Demonstration Boards PICDEM 1 ...
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... Precision Internal Oscillator Parameters........................... 120 Prescaler Shared WDT/Timer0 ................................................... 40 Switching Prescaler Assignment................................. 40 PRO MATE II Universal Device Programmer ................... 105 Product Identification ........................................................ 145 Program Memory Organization ............................................. 7 Map and Stack for the PIC12F683................................ 7 Programming, Device Instructions ...................................... 95 Pulse Width Modulation. See Capture/Compare/PWM, PWM Mode. R Read-Modify-Write Operations ........................................... 95 Registers ADCON0 (A/D Control) ...
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... PIC12F683 Timer2 ................................................................................. 45 Associated Registers .................................................. 46 Interrupt....................................................................... 46 Operation .................................................................... 45 Postscaler ................................................................... 45 PR2 Register............................................................... 45 Prescaler ..................................................................... 45 TMR2 Register ............................................................ 45 TMR2 to PR2 Match Interrupt ..................................... 45 Timing Diagrams A/D Conversion (Normal Mode) ................................ 128 A/D Conversion (Sleep Mode) .................................. 129 Brown-out Detect (BOD) ........................................... 122 Brown-out Detect Situations ....................................... 80 Capture/Compare/PWM (CCP)................................. 125 CLKOUT and I/O....................................................... 121 External Clock ...
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... Microchip’s development systems software products. Plus, this line provides information on how customers ® ® can receive the most current upgrade kits. The Hot Line or Microsoft Numbers are: 1-800-755-2345 for U.S. and most of Canada and 1-480-792-7302 for the rest of the world. Preliminary PIC12F683 042003 DS41211B-page 143 ...
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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC12F683 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...
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... JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. 2004 Microchip Technology Inc. XXX Examples: Pattern a) PIC12F683-E/P 301 = Extended Temp., PDIP package, 20 MHz, QTP pattern #301 b) PIC12F683-I/SO = Industrial Temp., SOIC package, 20 MHz range DD ...
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... Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 02/17/04 2004 Microchip Technology Inc. ...