MPC8533E_11 FREESCALE [Freescale Semiconductor, Inc], MPC8533E_11 Datasheet - Page 106
MPC8533E_11
Manufacturer Part Number
MPC8533E_11
Description
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MPC8533E_11.pdf
(112 pages)
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System Design Information
21.9.1
If the JTAG interface and COP header will not be used, Freescale recommends the following connections:
Figure 64
106
•
•
TRST should be tied to HRESET through a 0-kΩ isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
the power-on reset flow. Freescale recommends that the COP header be designed into the system
as shown in
in case a JTAG interface may need to be wired onto the system in future debug situations.
No pull-up/pull-down is required for TDI, TMS, or TDO.
shows the COP connector physical pinout.
Termination of Unused Signals
MPC8533E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Figure
COP_CHKSTP_OUT
65. If this is not possible, the isolation resistor will allow future access to TRST
COP_RUN/STOP
COP_HRESET
COP_SRESET
Figure 64. COP Connector Physical Pinout
COP_TDO
COP_TMS
COP_TCK
COP_TDI
13
15
11
1
1
3
5
7
9
No pin
KEY
10
12
16
2
4
6
8
NC
COP_TRST
COP_VDD_SENSE
COP_CHKSTP_IN
NC
NC
GND
Freescale Semiconductor
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