MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 17

• Manufacturer Part Number: MPC8572CLPXARLD
• Description: MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

4.4
Table 7
At recommended operating conditions with
4.5
Note the following eTSEC FIFO mode maximum speed restrictions based on platform (CCB) frequency.
For FIFO GMII modes (both 8-bit and 16-bit) and 16-bit Encoded FIFO mode:
Freescale Semiconductor
At recommended operating conditions with LV
EC_GTX_CLK125 duty cycle
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for L/TV
2. Timing is guaranteed by design and characterization.
3. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation.
DDRCLK frequency
DDRCLK cycle time
DDRCLK rise and fall time
DDRCLK duty cycle
DDRCLK jitter
Notes:
1. Caution: The DDR complex clock to DDRCLK ratio settings must be chosen such that the resulting DDR complex
2. Rise and fall times for DDRCLK are measured at 0.6 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The DDRCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to
6. For spread spectrum clocking, guidelines are +0% to –1% down spread at a modulation rate between 20 kHz and
for L/TV
EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle
generated by the TSEC n _GTX_CLK. See
for 10Base-T and 100Base-T reference clock.
clock frequency does not exceed the maximum or minimum operating frequencies. Refer to
“DDR/DDRCLK PLL
allow cascade-connected PLL-based devices to track DDRCLK drivers with the specified jitter.
60 kHz on DDRCLK.
FIFO TX/RX clock frequency <= platform clock (CCB) frequency/4.2
provides the DDR clock (DDRCLK) AC timing specifications for the MPC8572E.
DDR Clock Timing
Platform to eTSEC FIFO Restrictions
DD
Parameter/Condition
Parameter/Condition
=3.3V.
1000Base-T for RGMII, RTBI
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Table 6. EC_GTX_CLK125 AC Timing Specifications (continued)
Ratio,” for ratio settings.
Table 7. DDRCLK AC Timing Specifications
GMII, TBI
OV
DD
DD
/TV
of 3.3V ± 5%.
DD
of 3.3V ± 5% or 2.5V ± 5% (continued)
Section 8.2.6, “RGMII and RTBI AC Timing Specifications,”
t
t
KHK
G125H
Symbol
Symbol
f
t
t
DDRCLK
DDRCLK
KH
/t
—
DDRCLK
, t
/t
KL
G125
10.0
Min
Min
0.6
45
47
66
40
—
Typical
Typical
1.0
—
—
—
—
—
DD
+/– 150
=2.5V, and from 0.6V and 2.7V
15.15
Max
Max
100
1.2
55
53
60
Section 19.4,
Unit
Unit
MHz
ns
ns
ps
%
%
for duty cycle
Notes
Notes
4, 5, 6
Input Clocks
2, 3
—
1
2
3
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