MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 37

• Manufacturer Part Number: MPC8572CLPXARLD
• Description: MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

At recommended operating conditions with LV
Figure 15
8.2.4.2
Table 31
Freescale Semiconductor
Clock period for TBI Receive Clock 0, 1
Skew for TBI Receive Clock 0, 1
Duty cycle for TBI Receive Clock 0, 1
RCG[9:0] setup time to rising edge of TBI Receive Clock 0, 1
RCG[9:0] hold time to rising edge of TBI Receive Clock 0, 1
Clock rise time (20%-80%) for TBI Receive Clock 0, 1
Clock fall time (80%-20%) for TBI Receive Clock 0, 1
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. Guaranteed by design.
3. The signals “TBI Receive Clock 0” and “TBI Receive Clock 1” refer to TSECn_RX_CLK and TSECn_TX_CLK pins respectively.
for inputs and t
timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
to the high (H) state or setup time. Also, t
(D) went invalid (X) relative to the t
symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of
t
R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX).
These two clock signals are also referred as PMA_RX_CLK[0:1].
TRX
represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:
provides the TBI receive AC timing specifications.
shows the TBI transmit AC timing diagram.
TBI Receive AC Timing Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter/Condition
GTX_CLK
TCG[9:0]
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Table 31. TBI Receive AC Timing Specifications
TRX
Figure 15. TBI Transmit AC Timing Diagram
t
TTXH
DD
3
clock reference (K) going to the high (H) state. Note that, in general, the clock reference
t
TTKHDV
TRDXKH
/TV
t
TTXF
DD
t
TTX
of 2.5/ 3.3 V ± 5%.
symbolizes TBI receive timing (TR) with respect to the time data input signals
t
Symbol
TRXH
t
t
t
TRDVKH
TRDXKH
t
t
SKTRX
TRXR
TRXF
t
t
TRX
TTXF
/t
TRX
2
2
for outputs. For example, t
1
(first two letters of functional block)(signal)(state) (reference)(state)
t
TTKHDX
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
t
TTXR
Min
7.5
2.5
1.5
0.7
0.7
40
—
t
TTXR
16.0
Typ
—
—
—
—
—
—
TRDVKH
TRX
clock reference (K) going
symbolizes TBI receive
Max
8.5
2.4
2.4
60
—
—
—
Unit
ns
ns
ns
ns
ns
ns
%
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