MPC870 FREESCALE [Freescale Semiconductor, Inc], MPC870 Datasheet - Page 36

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MPC870

Manufacturer Part Number
MPC870
Description
Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Bus Signal Timing
Table 11
Figure 24
Figure 25
36
1
The I39 and I40 timings describe the testing conditions under which the IRQ lines are tested when being defined as
Num
level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference
to the CLKOUT.
The I41, I42, and I43 timings are specified to allow correct functioning of the IRQ lines detection circuitry and have
no direct relation with the total system interrupt latency that the MPC875/870 is able to support.
I39
I40
I41
I42
I43
provides the interrupt timing for the MPC875/870.
CLKOUT
CLKOUT
provides the interrupt detection timing for the external level-sensitive lines.
provides the interrupt detection timing for the external edge-sensitive lines.
IRQx
IRQx
IRQx valid to CLKOUT rising edge (setup time)
IRQx hold time after CLKOUT
IRQx pulse width low
IRQx pulse width high
IRQx edge-to-edge time
Figure 24. Interrupt Detection Timing for External Level Sensitive Lines
Figure 25. Interrupt Detection Timing for External Edge-Sensitive Lines
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MPC875/MPC870 Hardware Specifications, Rev. 3.0
Characteristic
Table 11. Interrupt Timing
1
I43
I39
I41
I40
I43
6.00
2.00
3.00
3.00
4xT
I42
CLOCKOUT
All Frequencies
Min
Freescale Semiconductor
Max
ns
ns
ns
ns
Unit

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