NS486SXL NSC [National Semiconductor], NS486SXL Datasheet - Page 10

• Manufacturer Part Number: NS486SXL
• Description: Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems
• Manufacturer: NSC [National Semiconductor]

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RAS[1:0]
CASH[1:0]
CASL[1:0]
WE
DPH, DPL
V
V
RESET
RESET
PWGOOD
CS[0]
CS[8:1]
DD
SS
2.0 SXL Pin Description Tables
Symbol
Symbol
Symbol
Symbol
72, 98, 113, 124
43, 44, 45, 63,
64, 65, 66, 67
2, 12, 24, 39,
9, 21, 37, 69,
95, 110, 121,
118, 129
15, 16
10, 11
13, 14
Pins
Pins
Pins
Pins
131
17
70
71
36
68
Ground
Power
Type
Type
Type
Type
I/O
O
O
O
O
O
O
O
O
I
TABLE 6. General Purpose Chip Select Pins
TABLE 3. DRAM Control Pins (Continued)
Row Address Strobe. On the falling edge of these active-low signals, Bank 1 and
Bank 0 respectively, should latch in the row address off of SA[12:1]. If only one
bank of DRAM is supported, RAS0 will support that bank and RAS1 will be
unused
Column Address Strobe (High Byte). These active-low signals indicate when the
column access is being made to the high byte of DRAM Bank 1 and DRAM Bank
0 respectively. If only one bank of DRAM is supported, CASH0 will support the
high byte of that bank and CASH1 will be unused.
Column Address Strobe (Low Byte). These active-low signals indicate when the
column access is being made to the low byte of DRAM Bank 1 and DRAM Bank
0, respectively. If only one bank of DRAM is supported, CASL0 will support the
low byte of that bank and CASL1 will be unused.
Write Enable. Active low signal for write operations on DRAM.
DRAM Data Parity. DRAM data parity may be enabled or disabled; if disabled
these two pins will be unused. Otherwise, for DRAM writes the SXL’s DRAM
Controller will generate odd parity and drive the odd parity onto these two pins.
For DRAM reads the SXL’s DRAM Controller will read the values driven on these
two pins and check it for odd parity in association with the appropriate data byte.
+5V power to core and I/O.
Ground to core and I/O.
RESET system output driver: This active high signal resets or initializes system
peripheral logic during power up (PWGOOD) or due to a WATCHDOG Reset.
Inverse of RESET for peripherals requiring active low reset.
PoWer GOOD. This active-high (schmitt trigger) input will cause a hardware reset
to the NS486SXL whenever this input goes low. This pin will typically be driven by
the power supply and PWGOOD will remain low until the power supply
determines that stable and valid voltage levels have been achieved.
Chip Select 0: This output is used as the chip-select for the system boot ROM. It
defaults to the upper 64k Bytes of memory.
Chip Select 1 to 8. These pins can be programmed to be either memory or I/ O
mapped chip selects, which are used for glueless connection to external
peripherals.
TABLE 5. Reset Logic Pins
TABLE 4. Power Pins
(Continued)
10
Function
Function
Function
Function