NS486SXL NSC [National Semiconductor], NS486SXL Datasheet - Page 9

• Manufacturer Part Number: NS486SXL
• Description: Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems
• Manufacturer: NSC [National Semiconductor]

BDIR
IOR
IOW
MEMR
MEMW
CS16
RDY
HOLD
HLDA
MAE
2.0 SXL Pin Description Tables
Symbol
Symbol
Pins
Pins
78
77
80
79
74
75
50
51
49
8
Type
Type
I/O
I/O
I/O
I/O
I/O
I/O
TABLE 1. Bus Interface Unit Pins (Continued)
O
O
O
TABLE 2. External Bus Master Interface Pins
I
Buffer DIRection. This output is provided to reduce external logic if an external
data-bus buffer is required in the user’s design. The BDIR signal is high whenever
the buffer should be driving from the ’SXL pins out to the buffered ISA-like bus.
BDIR also works correctly if an External Master is designed into the system,
however, the External Master must always be on the buffered side of the bus in
this case.
BDIR will only go low during reads from the buffered bus, or accesses to internal
peripherals or DRAM by an External Master.
IO Read command. This active-low signal instructs an I/O device to place data
onto the system data bus. An input when an External Master controls the bus.
IO Write command. This active-low signal indicates to an I/O device that a write
operation is in process on the system bus. An input when an External Master
controls the bus.
MEMory Read command. This active-low signal instructs a memory mapped
device to place data onto the system data bus. An input when an External Master
controls the bus.
MEMory Write command. This active-low signal indicates to a memory mapped
device that a write operation is in process on the system bus. An input when an
External Master controls the bus.
Chip Select 16-bit. This active-low feedback signal indicates that the device being
accessed is a 16-bit device. This signal should be pulled-up and driven by
external devices with an open collector driver. If a chip select is programmed to
force 16-bit accesses, this signal will be asserted (low) during the access. When
an External Master controls the bus, the ’SXL will also drive this signal low for
accesses to internal peripherals or DRAM.
ReaDY. An external device may drive this signal inactive low to insert wait states
and extend the external bus cycle. This signal should be pulled-up and driven with
an open collector or be TRI-STATE driven. When an External Master controls the
bus, it must honor the RDY signal as the ’SXL will drive this signal low as
appropriate for accesses to internal peripherals or DRAM and bus snooping.
HOLD Request from External Master. The external master will assert this signal
high in order to request the bus from the ’SXL CPU. The external master can hold
the bus indefinitely, so care should be taken to ensure that the HOLD is released
in time for the CPU to service any real-time requirements (e.g. Interrupts, etc.).
HoLD Acknowledge from ’SXL. When the ’SXL CPU grants the bus to an external
master, then this signal is asserted (low). Once HLDA is asserted, the external
master is responsible for driving the address and control signals (MEMR, MEMW,
IOR, IOW, SBHE) on the bus. If there are bi-directional buffers on the address
and control lines, then HLDA should be used to set the direction of the buffers.
Master Address Enable. During HLDA, if the ’SXL requires that the External
Master TRI-STATE its addresses (e.g. to complete a DRAM access) then MAE
will be de-asserted (high). MAE should be used to control the External Master’s
TRI-STATE address lines or for the enable of the bi-directional address bus buffer
chips. MAE will normally be asserted (low).
TABLE 3. DRAM Control Pins
(Continued)
9
Function
Function
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