LUPA-1300 CYPRESS [Cypress Semiconductor], LUPA-1300 Datasheet - Page 24

• Manufacturer Part Number: LUPA-1300
• Description: 1.3 M Pixel High Speed CMOS Image Sensor
• Manufacturer: CYPRESS [Cypress Semiconductor]

3.8.2 Biasing and analog signals
Besides the biasing signals, the only analog signals are the output signals Out1 –
Out16. Each output signal is analog with respect to the voltage level, but is discrete
in time. This means that on the speed of Clock_x, the outputs change to a different
level, depending on the illumination of the corresponding pixels.
The biasing signals determine the speed and power dissipation of the different
modules on chip. These biasing signals have to be connected trough a resistor to
ground or power supply and should be decoupled with a capacitor. If the sensor is
working properly, each of the biasing signals will have a dc-voltage depending on the
resistor value and on the internal circuitry. These dc-voltages can be used to check
the operation of the image sensor. Table 8 gives the different biasing signals, the way
they should be connected, and the expected dc-voltage.
variations, these dc-voltages change from chip to chip and 10% variation is possible.
Each resistor controls the speed and power dissipation of the corresponding module,
as this resistor determines the current required to charge and/or discharge internal
nodes inside the module.
A decoupling with a small capacitor is advisable to reduce the HF noise onto the
analog signals. Only the capacitor on the Pre_load signal can be omitted.
3.8.3 Pixel array signals
Figure 4 in paragraph 2.2 is a schematic representation of the pixel as used in the
LUPA design.
Cypress Semiconductor Corporation
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Pre_load
Col_load
Psf_load
Nsf_load
Load_out
Decx_load Connect with 27K
Decy_load Connect with 27K
Signal
LUPA-1300
Datasheet
Connect with 10K
to Gnd
Connect with 2M
Gnd
Connect with 240K
to Vdda
Connect with 100K
to Gnd
Connect with 27K
Gnd
Vdd
Vdd
The applied signals to this pixel are: reset, sample, Precharge,
Table 8 : overview of biasing signals
Document # : 38-05711 Rev.**( Revision 3.1)
3901 North First Street
Ω
Ω
Ω
Ω
Ω
Ω
Ω
to Vdda and capacitor of 100nF to
to Gnd and capacitor of 100nF to
to Gnd and capacitor of 100nF to
to Voo and capacitor of 100nF to
to Vdda and capacitor of 100nF
Comment
to Vdda and capacitor of 100nF
to Gnd and capacitor of 100nF
San Jose, CA 95134
Due to small process
Page 24 of 48
408-943-2600
Expected dc-
level
2.0V
0.9V
3.7V
1.3V
1.6V
2.8V
2.8V