MC68HC11F1CFN5 MOTOROLA [Motorola, Inc], MC68HC11F1CFN5 Datasheet - Page 23

• Manufacturer Part Number: MC68HC11F1CFN5
• Description: Technical Summary 8-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

CWOM — Port C Wired-OR Mode Option
CLK4X — 4XCLK Output Enable
LIRDV — Load Instruction Register Driven
Bits 3, 1, 0 — Not implemented. Reads always return zero and writes have no effect.
SPRBYP — See 10.2 SPI Registers, page 52.
OPTION — System Configuration Options
ADPU — A/D Power-Up
CSEL — Clock Select
IRQE — IRQ Select Edge Sensitive Only
DLY — Enable Oscillator Start-Up Delay on Exit from STOP
CME — Clock Monitor Enable
FCME — Force Clock Monitor Enable
CR[1:0] — COP Timer Rate Select
MC68HC11F1/FC0
MC68HC11FTS/D
RESET:
Refer to 7.8 Parallel I/O Registers, page 37.
This bit can only be written once after reset in all modes.
In order to detect consecutive instructions in a high-speed application, LIR can be driven high for one
quarter of an E-clock cycle during each instruction fetch.
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes.
This bit is implemented on the MC68HC11F1 only. On the MC68HC11FC0, reads always return zero
and writes have no effect.
This bit is implemented on the MC68HC11F1 only. On the MC68HC11FC0, reads always return zero
and writes have no effect.
In order to use both STOP and the clock monitor, the CME bit should be written to zero prior to executing
a STOP instruction and rewritten to one after recovery from STOP. FCME should be kept cleared if the
user intends to use the STOP instruction.
Refer to 5.2 Reset and Interrupt Registers, page 27.
0 = 4XOUT clock output is disabled
1 = Buffered oscillator is driven on the 4XOUT clock output
0 = LIR signal is not driven high.
1 = LIR signal is driven high.
0 = A/D system disabled
1 = A/D system enabled
0 = A/D and EEPROM use system E clock
1 = A/D and EEPROM use internal RC clock
0 = Low level recognition
1 = Falling edge recognition
0 = No stabilization delay on exit from STOP
1 = Stabilization delay of 4064 E-clock cycles is enabled on exit from STOP
0 = Clock monitor disabled; slow clocks can be used
1 = Slow or stopped clocks cause clock failure reset
0 = Clock monitor circuit follows the state of the CME bit
1 = Clock monitor circuit is enabled until the next reset
ADPU
Bit 7
0
CSEL
6
0
IRQE*
5
0
DLY*
4
1
CME
3
0
FCME*
2
0
CR1*
1
0
CR0*
Bit 0
0
MOTOROLA
$x039
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