MC68HC11F1CFN5 MOTOROLA [Motorola, Inc], MC68HC11F1CFN5 Datasheet - Page 53

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MC68HC11F1CFN5

Manufacturer Part Number
MC68HC11F1CFN5
Description
Technical Summary 8-Bit Microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet

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11 Analog-to-Digital Converter
MC68HC11F1/FC0
MC68HC11FTS/D
PE0
AN0
PE1
AN1
PE2
AN2
PE6
AN6
PE7
AN7
PE3
AN3
PE4
AN4
PE5
AN5
The MC68HC11F1 analog-to-digital (A/D) converter system uses an all-capacitive charge-redistribution
technique to convert analog signals to digital values. The A/D system is an 8-channel, 8-bit, multiplexed-
input, successive-approximation converter, accurate to 1 least significant bit (LSB). Because the ca-
pacitive charge redistribution technique used includes a built-in sample-and-hold, no external sample-
and-hold is required.
Dedicated lines V
rates of 750 kHz or below must use an internal RC oscillator. The CSEL bit in the OPTION register se-
lects the clock source for the A/D system. (The CSEL bit is described in 11.3 A/D Registers, page 56.)
A multiplexer allows the single A/D converter to select one of 16 analog signals, as shown in Table 24.
ANALOG
ADR1 A/D RESULT 1
MUX
RH
and V
The A/D converter is present on the MC68HC11F1 only.
RESULT
RL
Figure 14 A/D Converter Block Diagram
ADR2 A/D RESULT 2
provide the reference supply voltage inputs. Systems operating at clock
SUCCESSIVE APPROXIMATION
WITH SAMPLE AND HOLD
REGISTER AND CONTROL
8-BIT CAPACITIVE DAC
RESULT REGISTER INTERFACE
NOTE
ADR3 A/D RESULT 3
ADCTL A/D CONTROL
ADR4 A/D RESULT 4
V
V
RH
RL
INTERNAL
DATA BUS
MOTOROLA
EA9 A/D BLOCK
53

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