PIC18F2221 MICROCHIP [Microchip Technology], PIC18F2221 Datasheet - Page 178

• Manufacturer Part Number: PIC18F2221
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

corresponding address bit is ignored (ADD<n> = x). For
PIC18F4321 FAMILY
17.4.3.2
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an inter-
rupt. It is possible to mask more than one address bit at
a time, which makes it possible to Acknowledge up to
31 addresses in 7-bit Addressing mode and up to 63
addresses
Example 17-2).
The I
masking is used or not. However, when address mask-
ing is used, the I
addresses and cause interrupts. When this occurs, it is
necessary to determine which address caused the
interrupt by checking the SSPBUF register.
• 7-bit Address mode
Address mask bits, ADMSK<5:1>, mask the corre-
sponding address bits in the SSPADD register. For any
ADMSK bits that are active (ADMSK<n> = 1), the
the module to issue an address Acknowledge, it is suffi-
cient to match only on addresses that do not have an
active address mask.
EXAMPLE 17-2:
DS39689E-page 176
7-bit Addressing mode:
10-bit Addressing mode:
2
C slave behaves the same way whether address
SSPADD<7:1> = 1010 0000
ADMSK<5:1> = 00 111
Addresses Acknowledged = 0xA0, 0xA2, 0xA4, 0xA6, 0xA8, 0xAA, 0xAC, 0xAE
SSPADD<7:0> = 1010 0000 (The two MSbs are ignored in this example since they are not affected)
ADMSK<5:1> = 00 111
Addresses Acknowledged = 0xA0, 0xA1, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xAB,
The upper two bits are not affected by the address masking.
in
Address Masking
2
10-bit
C slave can Acknowledge multiple
ADDRESS MASKING
Addressing
0xAC, 0xAD, 0xAE, 0xAF
mode
(see
Preliminary
• 10-bit Address mode
Address
corresponding address bits in the SSPADD register. In
addition, ADMSK<1> simultaneously masks the two
LSBs of the address, ADD<1:0>. For any ADMSK bits
that are active (ADMSK<n> = 1), the corresponding
address bit is ignored (ADD<n> = x). Also note that
although in 10-bit Addressing mode, the upper address
bits reuse part of the SSPADD register bits, the address
mask bits do not interact with those bits. They only
affect the lower address bits.
Note 1: ADMSK<1>
2: The two Most Significant bits of the
mask
Significant bits of the address.
address are not affected by address
masking.
bits,
© 2007 Microchip Technology Inc.
ADMSK<5:2>,
masks
the
two
mask
Least
the