PIC18F2221 MICROCHIP [Microchip Technology], PIC18F2221 Datasheet - Page 386

• Manufacturer Part Number: PIC18F2221
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F4321 FAMILY
H
Hardware Multiplier ............................................................ 89
High/Low-Voltage Detect ................................................. 247
HLVD. See High/Low-Voltage Detect.
I
I/O Ports ........................................................................... 105
I
ID Locations ............................................................. 253, 271
INCF ................................................................................. 294
INCFSZ ............................................................................ 295
In-Circuit Debugger .......................................................... 271
In-Circuit Serial Programming (ICSP) ...................... 253, 271
DS39689E-page 384
2
C Mode (MSSP)
Introduction ................................................................ 89
Operation ................................................................... 89
Performance Comparison .......................................... 89
Applications .............................................................. 250
Associated Registers ............................................... 251
Characteristics ......................................................... 344
Current Consumption ............................................... 249
Effects of a Reset ..................................................... 251
Operation ................................................................. 248
Setup ........................................................................ 249
Start-up Time ........................................................... 249
Typical Application ................................................... 250
Acknowledge Sequence Timing ............................... 198
Associated Registers ............................................... 204
Baud Rate Generator ............................................... 191
Bus Collision
Clock Arbitration ....................................................... 192
Clock Stretching ....................................................... 184
Clock Synchronization and the CKP Bit ................... 185
Effects of a Reset ..................................................... 199
General Call Address Support ................................. 188
I
Master Mode ............................................................ 189
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 199
Operation ................................................................. 175
Read/Write Bit
Read/Write Bit Information (R/W Bit) ....................... 177
Registers .................................................................. 170
Serial Clock (RC3/SCK/SCL) ................................... 177
Slave Mode .............................................................. 175
Sleep Operation ....................................................... 199
Stop Condition Timing .............................................. 198
2
C Clock Rate w/BRG ............................................. 191
During Sleep .................................................... 251
During a Repeated Start Condition .................. 202
During a Start Condition ................................... 200
During a Stop Condition ................................... 203
10-Bit Slave Receive Mode (SEN = 1) ............. 184
10-Bit Slave Transmit Mode ............................. 184
7-Bit Slave Receive Mode (SEN = 1) ............... 184
7-Bit Slave Transmit Mode ............................... 184
Operation ......................................................... 190
Reception ......................................................... 195
Repeated Start Condition Timing ..................... 194
Start Condition Timing ..................................... 193
Transmission .................................................... 195
and Arbitration .................................................. 199
Information (R/W Bit) ....................................... 175
Address Masking ............................................. 176
Addressing ....................................................... 175
Reception ......................................................... 177
Transmission .................................................... 177
Preliminary
Indexed Literal Offset Addressing
Indexed Literal Offset Mode ............................................. 320
Indirect Addressing ............................................................ 68
INFSNZ ............................................................................ 295
Initialization Conditions for all Registers ...................... 49–52
Instruction Cycle ................................................................ 57
Instruction Flow/Pipelining ................................................. 57
Instruction Set .................................................................. 273
and Standard PIC18 Instructions ............................. 320
Clocking Scheme ....................................................... 57
ADDLW .................................................................... 279
ADDWF .................................................................... 279
ADDWF (Indexed Literal Offset Mode) .................... 321
ADDWFC ................................................................. 280
ANDLW .................................................................... 280
ANDWF .................................................................... 281
BC ............................................................................ 281
BCF ......................................................................... 282
BN ............................................................................ 282
BNC ......................................................................... 283
BNN ......................................................................... 283
BNOV ...................................................................... 284
BNZ ......................................................................... 284
BOV ......................................................................... 287
BRA ......................................................................... 285
BSF .......................................................................... 285
BSF (Indexed Literal Offset Mode) .......................... 321
BTFSC ..................................................................... 286
BTFSS ..................................................................... 286
BTG ......................................................................... 287
BZ ............................................................................ 288
CALL ........................................................................ 288
CLRF ....................................................................... 289
CLRWDT ................................................................. 289
COMF ...................................................................... 290
CPFSEQ .................................................................. 290
CPFSGT .................................................................. 291
CPFSLT ................................................................... 291
DAW ........................................................................ 292
DCFSNZ .................................................................. 293
DECF ....................................................................... 292
DECFSZ .................................................................. 293
Extended Instruction Set ......................................... 315
General Format ........................................................ 275
GOTO ...................................................................... 294
INCF ........................................................................ 294
INCFSZ .................................................................... 295
INFSNZ .................................................................... 295
IORLW ..................................................................... 296
IORWF ..................................................................... 296
LFSR ....................................................................... 297
MOVF ...................................................................... 297
MOVFF .................................................................... 298
MOVLB .................................................................... 298
MOVLW ................................................................... 299
MOVWF ................................................................... 299
MULLW .................................................................... 300
MULWF .................................................................... 300
NEGF ....................................................................... 301
NOP ......................................................................... 301
Opcode Field Descriptions ....................................... 274
POP ......................................................................... 302
PUSH ....................................................................... 302
RCALL ..................................................................... 303
RESET ..................................................................... 303
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