MC68HC705BD3 FREESCALE [Freescale Semiconductor, Inc], MC68HC705BD3 Datasheet - Page 53

• Manufacturer Part Number: MC68HC705BD3
• Description: High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

7.3.3
Register bit definitions:
MEN - M-Bus Enable
MIEN - M-Bus Interrupt Enable
This bit enables the MIF (in MSR) for M-Bus interrupts.
MSTA - Master/Slave Select
Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is generated
on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP signal
is generated and the operation mode changes from master to slave. In master mode, a bit clear
immediately followed by a bit set of this bit generates a repeated START signal without generating
a STOP signal.
MTX - Transmit/Receive Mode Select
TXAK - Acknowledge Enable
If cleared, an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one
byte of data. If set, no acknowledge signal response. This is an active low control bit.
MC68HC05BD3
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Address
$0019
M-Bus Control Register (MCR)
MEN
–
–
–
–
–
bit 7
M-Bus interface system enabled.
M-Bus interface system disabled.
M-Bus interrupt enabled.
M-Bus interrupt disabled.
M-Bus is set for master mode operation.
M-Bus is set for slave mode operation.
M-Bus is set for transmit mode.
M-Bus is set for receive mode.
Do not send acknowledge signal.
Send acknowledge signal at 9th clock bit.
MIEN
bit 6
MSTA
bit 5
M-BUS SERIAL INTERFACE
bit 4
MTX
TXAK
bit 3
bit 2
bit 1
bit 0
0000 0000
on reset
State
TPG
7-7
7