MC68HC705BD3 FREESCALE [Freescale Semiconductor, Inc], MC68HC705BD3 Datasheet - Page 84

• Manufacturer Part Number: MC68HC705BD3
• Description: High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

9
9.3.4
In the extended addressing mode, the effective address of the argument is contained in the two
bytes following the opcode byte. Instructions with extended addressing mode are capable of
referencing arguments anywhere in memory with a single three-byte instruction. When using the
Motorola assembler, the user need not specify whether an instruction uses direct or extended
addressing. The assembler automatically selects the short form of the instruction.
9.3.5
In the indexed, no offset addressing mode, the effective address of the argument is contained in
the 8-bit index register. This addressing mode can access the first 256 memory locations. These
instructions are only one byte long. This mode is often used to move a pointer through a table or
to hold the address of a frequently referenced RAM or I/O location.
9.3.6
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the
operand can be located anywhere within the lowest 511 memory locations. This addressing mode
is useful for selecting the mth element in an n element table.
9.3.7
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address
mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction
allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola
assembler determines the shortest form of indexed addressing.
9-12
Extended
Indexed, no offset
Indexed, 8-bit offset
Indexed, 16-bit offset
Address bus high
Address bus high
where K = the carry from the addition of X and (PC+1)
where K = the carry from the addition of X and (PC+2)
Address bus high
Address bus high
CPU CORE AND INSTRUCTION SET
EA = X+[(PC+1):(PC+2)]; PC
EA = (PC+1):(PC+2); PC
EA = X+(PC+1); PC
EA = X; PC
(PC+1)+K; Address bus low
(PC+1); Address bus low
K; Address bus low
0; Address bus low
PC+1
PC+2
PC+3
PC+3
X+(PC+1)
X
(PC+2)
X+(PC+2)
MC68HC05BD3
TPG