ENC28J60-C/ML MICROCHIP [Microchip Technology], ENC28J60-C/ML Datasheet - Page 39

• Manufacturer Part Number: ENC28J60-C/ML
• Description: Stand-Alone Ethernet Controller with SPI Interface
• Manufacturer: MICROCHIP [Microchip Technology]

6.6
Depending on the application, bits in three of the PHY
module’s registers may also require configuration.
The PHCON1.PDPXMD bit partially controls the
device’s half/full-duplex configuration. Normally, this bit
is initialized correctly by the external circuitry (see
Section 2.6 “LED Configuration”). If the external
circuitry is not present or incorrect, however, the host
controller must program the bit properly. Alternatively,
for an externally configurable system, the PDPXMD bit
may be read and the FULDPX bit be programmed to
match.
For proper duplex operation, the PHCON1.PDPXMD
bit must also match the value of the MACON3.FULDPX
bit.
REGISTER 6-5:
© 2006 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-11
bit 10
bit 9
bit 8
bit 7-0
R/W-0
U-0
—
r
PHY Initialization Settings
Unimplemented: Read as ‘0’
FRCLNK: PHY Force Linkup bit
1 = Force linkup even when no link partner is detected
0 = Normal operation
TXDIS: Twisted-Pair Transmitter Disable bit
1 = Disable twisted-pair transmitter
0 = Normal operation
Reserved: Write as ‘0’
JABBER: Jabber Correction Disable bit
1 = Disable jabber correction
0 = Normal operation
Reserved: Write as ‘0’
HDLDIS: PHY Half-Duplex Loopback Disable bit
When PHCON1<8> = 1 or PHCON1<14> = 1:
This bit is ignored.
When PHCON1<8> = 0 and PHCON1<14> = 0:
1 = Transmitted data will only be sent out on the twisted-pair interface
0 = Transmitted data will be looped back to the MAC and sent out on the twisted-pair interface
Reserved: Write as ‘0’
FRCLNK
R/W-0
R/W-0
r
PHCON2: PHY CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
TXDIS
R/W-0
R/W-0
r
R/W-0
R/W-0
Preliminary
r
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
R/W-0
If using half duplex, the host controller may wish to set
the PHCON2.HDLDIS bit to prevent automatic
loopback of the data which is transmitted.
The PHY register, PHLCON, controls the outputs of
LEDA and LEDB. If an application requires a LED
configuration other than the default, PHLCON must be
altered to match the new requirements. The settings for
LED operation are discussed in Section 2.6 “LED
Configuration”. The PHLCON register is shown in
Register 2-2 (page 9).
r
r
JABBER
R/W-0
R/W-0
r
x = Bit is unknown
ENC28J60
R/W-0
R/W-0
r
r
DS39662B-page 37
HDLDIS
R/W-0
R/W-0
r
bit 8
bit 0