ENC28J60-C/ML MICROCHIP [Microchip Technology], ENC28J60-C/ML Datasheet - Page 5

• Manufacturer Part Number: ENC28J60-C/ML
• Description: Stand-Alone Ethernet Controller with SPI Interface
• Manufacturer: MICROCHIP [Microchip Technology]

1.0
The ENC28J60 is a stand-alone Ethernet controller
with an industry standard Serial Peripheral Interface
(SPI). It is designed to serve as an Ethernet network
interface for any controller equipped with SPI.
The ENC28J60 meets all of the IEEE 802.3 specifica-
tions. It incorporates a number of packet filtering
schemes to limit incoming packets. It also provides an
internal DMA module for fast data throughput and hard-
ware assisted checksum calculation, which is used in
various network protocols. Communication with the
host controller is implemented via an interrupt pin and
the SPI, with clock rates of up to 20 MHz. Two dedi-
cated pins are used for LED link and network activity
indication.
A simple block diagram of the ENC28J60 is shown in
Figure 1-1. A typical application circuit using the device
is shown in Figure 1-2. With the ENC28J60, two pulse
transformers and a few passive components are all that
is required to connect a microcontroller to an Ethernet
network.
FIGURE 1-1:
© 2006 Microchip Technology Inc.
CLKOUT
Note 1:
SCK
CS
INT
SI
SO
(1)
(1)
(1)
OVERVIEW
These pins are 5V tolerant.
Bus Interface
Registers
Control
SPI
Dual Port RAM
ENC28J60 BLOCK DIAGRAM
8 Kbytes
Buffer
Arbiter
ch0
ch1
System Control
RESET
(1)
Preliminary
ch0
ch1
Host Interface
Power-on
Flow Control
RXF (Filter)
Checksum
Reset
The ENC28J60 consists of seven major functional
blocks:
1.
2.
3.
4.
5.
6.
7.
The device also contains other support blocks, such as
the oscillator, on-chip voltage regulator, level translators
to provide 5V tolerant I/Os and system control logic.
RXBM
DMA &
TXBM
RX
TX
An SPI interface that serves as a communica-
tion channel between the host controller and the
ENC28J60.
Control Registers which are used to control and
monitor the ENC28J60.
A dual port RAM buffer for received and
transmitted data packets.
An arbiter to control the access to the RAM
buffer when requests are made from DMA,
transmit and receive blocks.
The bus interface that interprets data and
commands received via the SPI interface.
The MAC (Medium Access Control) module that
implements IEEE 802.3 compliant MAC logic.
The PHY (Physical Layer) module that encodes
and decodes the analog data that is present on
the twisted pair interface.
Regulator
Voltage
V
CAP
MAC
Interface
Interface
MIIM
MII
ENC28J60
Oscillator
25 MHz
PHY
DS39662B-page 3
TX
RX
TPOUT+
TPOUT-
RBIAS
LEDB
TPIN+
TPIN-
LEDA
OSC1
OSC2